Eiji Fujiwara

Publication Activity (10 Years)

Years Active: 1982-2010
Publications (10 Years): 0

Publications

Kazuyoshi Suzuki, Eiji Fujiwara
MacWilliams Identity for M-Spotty Weight Enumerator. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2010)
Haruhiko Kaneko, Eiji Fujiwara
A Class of Array Codes Correcting a Cluster of Unidirectional Errors for Two-Dimensional Matrix Symbols. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (6) (2009)
Haruhiko Kaneko, Eiji Fujiwara
Joint source-cryptographic-channel coding for dependable systems. Int. J. Comput. Appl. Technol. 34 (4) (2009)
Haruhiko Kaneko, Eiji Fujiwara
-Ary Substitution/Deletion/Insertion/Adjacent-Symbol-Transposition Error Correcting Codes for Data Entry Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2009)
Haruhiko Kaneko, Takuya Matsuzaka, Eiji Fujiwara
Three-Level Error Control Coding for Dependable Solid-State Drives. PRDC (2008)
Kazuyoshi Suzuki, Toshihiko Kashiyama, Eiji Fujiwara
A General Class of M-Spotty Byte Error Control Codes. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2007)
Kazuyoshi Suzuki, Haruhiko Kaneko, Eiji Fujiwara
Mac Williams Identity for m-Spotty Weight Enumerator. ISIT (2007)
Haruhiko Kaneko, Eiji Fujiwara
Reconstruction of Erasure Correcting Codes for Dependable Distributed Storage System without Spare Disks. DFT (2007)
Haruhiko Kaneko, Eiji Fujiwara
Joint Source-Cryptographic-Channel Coding Based on Linear Block Codes. AAECC (2007)
Kazuteru Namba, Eiji Fujiwara
Nonbinary single-symbol error correcting, adjacent two-symbol transposition error correcting codes over integer rings. Systems and Computers in Japan 38 (8) (2007)
Hiroyuki Ohde, Haruhiko Kaneko, Eiji Fujiwara
Low-Density Triple-Erasure Correcting Codes for Dependable Distributed Storage Systems. DFT (2006)
Kazuyoshi Suzuki, Toshihiko Kashiyama, Eiji Fujiwara
Complex M-Spotty Byte Error Control Codes. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (9) (2006)
Jien-Chung Lo, Yu-Lun Wan, Eiji Fujiwara
Transient Behavior of the Encoding/Decoding Circuits of Error Correcting Codes. DFT (2005)
Kazuyoshi Suzuki, Mamoru Shimizu, Toshihiko Kashiyama, Eiji Fujiwara
A class of error control codes for M-spotty byte errors occurred in a limited number of bytes. ISIT (2005)
Kazuyoshi Suzuki, Toshihiko Kashiyama, Eiji Fujiwara
Complex M-spotty byte error control codes. ITW (2005)
Ganesan Umanesan, Eiji Fujiwara
Parallel Decoding Cyclic Burst Error Correcting Codes. IEEE Trans. Computers 54 (1) (2005)
Haruhiko Kaneko, Mariko Numakami, Eiji Fujiwara
Nonsystematic M-Ary Asymmetric Error Correcting Codes Designed by Multilevel Coding Method. PRDC (2004)
Haruhiko Kaneko, Eiji Fujiwara
A Class of M-Ary Asymmetric Symbol Error Correcting Codes for Data Entry Devices. IEEE Trans. Computers 53 (2) (2004)
Ganesan Umanesan, Eiji Fujiwara
A Class of Codes for Correcting Single Spotty Byte Errors. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (3) (2003)
Ganesan Umanesan, Eiji Fujiwara
A Class of Random Multiple Bits in a Byte Error Correcting and Single Byte Error Detecting (S_t/b EC-S_bED) Codes. IEEE Trans. Computers 52 (7) (2003)
Haruhiko Kaneko, Eiji Fujiwara
Array Codes Correcting a Cluster of Unidirectional Errors for Two-Dimensional Matrix Symbols. DFT (2003)
Ganesan Umanesan, Eiji Fujiwara
Single Byte Error Correcting Codes with Double Bit within a Block Error Correcting Capability for Memory Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2002)
Ganesan Umanesan, Eiji Fujiwara
EC) Codes for Memory Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (1) (2002)
Ganesan Umanesan, Eiji Fujiwara
Adjacent Double Bit Error Correcting Codes with Single Byte Error Detecting Capability for Memory Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2002)
Ganesan Umanesan, Eiji Fujiwara
A Class of Random Multiple Bits in a Byte Error Correcting (S t/b EC)Codes for Semiconductor Memory Systems. PRDC (2002)
Kazuteru Namba, Eiji Fujiwara
Two-Level Unequal Error Protection Codes with Burst and Bit Error Correcting Capabilities. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (6) (2002)
Ganesan Umanesan, Eiji Fujiwara
A class of systematic t/B-error correcting codes for semiconductor memory systems. ITW (2001)
Kazuteru Namba, Eiji Fujiwara
Unequal Error Protection Codes with Two-Level Burst and Bit Error Correcting Capabilities. DFT (2001)
Kazuteru Namba, Eiji Fujiwara
A class of systematic m-ary single-symbol error correcting codes. Systems and Computers in Japan 32 (6) (2001)
Ganesan Umanesan, Eiji Fujiwara
Single Byte Error Control Codes with Double Bit within a Block Error Correcting Capability for Semiconductor Memory Systems. DFT (2000)
Masato Kitakami, Hongyuan Chen, Eiji Fujiwara
Evaluations of Burst Error Recovery for VF Arithmetic Coding. DFT (2000)
Kiattichai Saowapa, Haruhiko Kaneko, Eiji Fujiwara
Systematic Deletion/Insertion Error Correcting Codes with Random Error Correction Capability. DFT (1999)
Eiji Fujiwara, Tepparit Ritthongpitak, Masato Kitakami
Optimal Two-Level Unequal Error Control Codes for Computer Systems. IEEE Trans. Computers 47 (12) (1998)
Mitsuru Hamada, Eiji Fujiwara
A Class of Error Control Codes for Byte Organized Memory Systems -SbEC-(Sb+S)ED Codes-. IEEE Trans. Computers 46 (1) (1997)
Jien-Chung Lo, Eiji Fujiwara
Probability to Achieve TSC Goal. IEEE Trans. Computers 45 (4) (1996)
Tepparit Ritthongpitak, Masato Kitakami, Eiji Fujiwara
Optimal Two-Level Unequal Error Control Codes for Computer Systems. FTCS (1996)
Jien-Chung Lo, Masato Kitakami, Eiji Fujiwara
Reliable Logic Circuits with Byte Error Control Codes: A Feasibility Study. DFT (1996)
Eiji Fujiwara, Masaharu Tanaka
Defect-Tolerant WSI File Memory System Using Address Permutation for Spare Allocation. IEICE Trans. Inf. Syst. (2) (1995)
Eiji Fujiwara, Tsuyoshi Tanaka
Fault-tolerant associate memories. Systems and Computers in Japan 26 (7) (1995)
Eiji Fujiwara, Masato Kitakami
A Class of Optimal Fixed-Byte Error Protection Codes for Computer Systems. FTCS (1995)
Eiji Fujiwara, Masato Kitakami
A class of error-correcting codes for byte-organized memory systems. IEEE Trans. Inf. Theory 40 (6) (1994)
Eiji Fujiwara, Masaharu Tanaka
A Defect-Tolerant WSI File Memory System Using Address Permutation Scheme for Spare Allocation. DFT (1993)
Jien-Chung Lo, Eiji Fujiwara
A Probabilistic Measurement for Totally Self-Checking Circuits. DFT (1993)
Eiji Fujiwara, Masato Kitakami
A Class of Error Locating Codes for Byte-Organized Memory Systems. FTCS (1993)
Eiji Fujiwara, Mitsuru Hamada
-Bit Byte Error Correcting and Double Bit Error Detecting Codes for High-Speed Memory Systems. FTCS (1992)
Eiji Fujiwara, Dhiraj K. Pradhan
Error-Control Coding in Computers. Computer 23 (7) (1990)
Eiji Fujiwara, Kohji Matsuoka
Fault - tolerant k - out - of - n logic unit networks. Systems and Computers in Japan 19 (9) (1988)
Kazumitsu Matsuzawa, Eiji Fujiwara
Masking asymmetric line faults using semi-distance codes. FTCS (1988)
Eiji Fujiwara, Kohji Matsuoka
A Self-Checking Generalized Prediction Checker and Its Use for Built-In Testing. IEEE Trans. Computers 36 (1) (1987)
Eiji Fujiwara, Nobuo Mutoh, Kohji Matsuoka
A Self-Testing Group-Parity Prediction Checker and Its Use for Built-In Testing. IEEE Trans. Computers 33 (6) (1984)
Shigeo Kaneda, Eiji Fujiwara
Single Byte Error Correcting - Double Byte Error Detecting Codes for Memory Systems. IEEE Trans. Computers 31 (7) (1982)