Jien-Chung Lo

Publication Activity (10 Years)

Years Active: 1988-2006
Publications (10 Years): 0

Publications

Chuen-Song Chen, Jien-Chung Lo, Tian Xia
An indirect current sensing technique for IDDQ and IDDT tests. ACM Great Lakes Symposium on VLSI (2006)
Jien-Chung Lo, Cecilia Metra, Fabrizio Lombardi
Guest Editors' Introduction: Special Section on Design and Test of Systems-on-Chip (SoC). IEEE Trans. Computers 55 (2) (2006)
Chuen-Song Chen, Jien-Chung Lo, Tian Xia
Equivalent IDDQ Tests for Systems with Regulated Power Supply. DFT (2006)
Jien-Chung Lo, Yu-Lun Wan, Eiji Fujiwara
Transient Behavior of the Encoding/Decoding Circuits of Error Correcting Codes. DFT (2005)
Tian Xia, Jien-Chung Lo
On-chip short-time interval measurement system for high-speed signal timing characterization. J. Syst. Archit. 51 (4) (2005)
Seok-Bum Ko, Jien-Chung Lo
Efficient Realization of Parity Prediction Functions in FPGAs. J. Electron. Test. 20 (5) (2004)
Tian Xia, Peilin Song, Keith A. Jenkins, Jien-Chung Lo
Delay chain based programmable jitter generator. ETS (2004)
Tian Xia, Jien-Chung Lo
On-Chip Short-Time Interval Measurement for High-Speed Signal Timing Characterization. Asian Test Symposium (2003)
Seok-Bum Ko, Jien-Chung Lo
A Novel Technology Mapping Method for AND/XOR Expressions. ISMVL (2003)
Tian Xia, Jien-Chung Lo
Time-to-voltage converter for on-chip jitter measurement. IEEE Trans. Instrum. Meas. 52 (6) (2003)
Seok-Bum Ko, Jien-Chung Lo
Efficient Decomposition Techniques for FPGAs. HiPC (2002)
Seok-Bum Ko, Yu-Yau Guo, Jien-Chung Lo
Studies of the SEMATECH IDDq test data. J. Syst. Archit. 47 (10) (2002)
Tian Xia, Jien-Chung Lo
On-Chip Jitter Measurement for Phase Locked Loops. DFT (2002)
Jien-Chung Lo
Analysis of a BICS-Only Concurrent Error Detection Method. IEEE Trans. Computers 51 (3) (2002)
Seok-Bum Ko, Tian Xia, Jien-Chung Lo
Efficient Parity Prediction in FPGA. DFT (2001)
Jien-Chung Lo, William D. Armitage, Corbet S. Johnson
Using Atomic Force Microscopy for Deep-Submicron Failure Analysis. IEEE Des. Test Comput. 18 (1) (2001)
Augustus K. Uht, Jien-Chung Lo, Ying Sun, James C. Daly, James Kowalski
Building Real Computer Systems. IEEE Micro 20 (3) (2000)
Cecilia Metra, Jien-Chung Lo
Intermediacy Prediction for High Speed Berger Code Checkers. J. Electron. Test. 16 (6) (2000)
Shengli Li, Kai Zhang, Jien-Chung Lo
The 2nd Order Analysis of IDDQ Test Data. DFT (2000)
William D. Armitage, Jien-Chung Lo
Erasure Error Correction with Hardware Detection. DFT (1999)
Yu-Yau Guo, Jien-Chung Lo
Challenges of Built-In Current Sensor Designs. DFT (1998)
Jien-Chung Lo
Highly Reliable Systems with Differential Built-In Current Sensors. DFT (1998)
Jien-Chung Lo
Online Current Testing. IEEE Des. Test Comput. 15 (4) (1998)
Jien-Chung Lo
Correction to "A Fast Binary Adder with Conditional Carry Generation" IEEE Transaction on Computers 46(2) 248-253 (1997). IEEE Trans. Computers 47 (12) (1998)
Jien-Chung Lo
A Case Study of Self-Checking Circuits Reliability. VLSI Design 1998 (4) (1998)
Jien-Chung Lo
A Fast Binary Adder with Conditional Carry Generation. IEEE Trans. Computers 46 (2) (1997)
Yu-Yau Guo, Jien-Chung Lo, Cecilia Metra
Fast and area-time efficient Berger code checkers. DFT (1997)
Jien-Chung Lo
A Hyper Optimal Encoding Scheme for Self-Checking Circuits. IEEE Trans. Computers 45 (9) (1996)
Jien-Chung Lo, Eiji Fujiwara
Probability to Achieve TSC Goal. IEEE Trans. Computers 45 (4) (1996)
Jien-Chung Lo, Masato Kitakami, Eiji Fujiwara
Reliable Logic Circuits with Byte Error Control Codes: A Feasibility Study. DFT (1996)
Peilin Song, Jien-Chung Lo
Test Sequence Generation for Realistic Faults in CMOS ICs Based on Standard Cell Library. DFT (1996)
Jien-Chung Lo, Suchai Thanawastien, T. R. N. Rao
Berger Check Prediction for Array Multipliers and Array Dividers. IEEE Trans. Computers 45 (3) (1996)
Jien-Chung Lo
Single fault masking logic designs with error correcting codes. DFT (1995)
Jien-Chung Lo, James C. Daly, Michael Nicolaidis
A strongly code disjoint built-in current sensor for strongly fault-secure static CMOS realizations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14 (11) (1995)
Jien-Chung Lo
Reliable Floating-Point Arithmetic Algorithms for Error-Coded Operands. IEEE Trans. Computers 43 (4) (1994)
Jien-Chung Lo, Shih-Yao Sun, James C. Daly
A concurrent error detection IC in 2-μm static CMOS logic. IEEE J. Solid State Circuits 29 (5) (1994)
Jien-Chung Lo
Fault-Tolerant Content Addressable Memory. ICCD (1993)
Jien-Chung Lo, Suchai Thanawastien, T. R. N. Rao
Berger Check Prediction for Array Multipliers and Array Dividers. IEEE Trans. Computers 42 (7) (1993)
Jien-Chung Lo, Eiji Fujiwara
A Probabilistic Measurement for Totally Self-Checking Circuits. DFT (1993)
T. R. N. Rao, Gui Liang Feng, Mahadev S. Kolluru, Jien-Chung Lo
Novel Totally Self-Checking Berger Code Checker Designs Based on Generalized Berger Code Partitioning. IEEE Trans. Computers 42 (8) (1993)
Jien-Chung Lo
Reliable Floating-Point Arithmetic Algorithms for Berger Encoded Operands. ICCD (1992)
Jien-Chung Lo, James C. Daly, Michael Nicolaidis
Design of Static CMOS Self-Checking Circuits using Built-In Current Sensing. FTCS (1992)
Tung-Li Shen, James C. Daly, Jien-Chung Lo
On-chip current sensing circuit for CMOS VLSI. VTS (1992)
Jien-Chung Lo, Suchai Thanawastien, T. R. N. Rao, Michael Nicolaidis
An SFS Berger check prediction ALU and its application to self-checking processor designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11 (4) (1992)
Hungshih Chang, Jien-Chung Lo
A new protocol for efficient bandwidth distribution in integrated service networks. LCN (1991)
Jien-Chung Lo, Suchai Thanawastien
On the Design of Combinational Totally Self-Checking I-out-of3 Code Checkers. IEEE Trans. Computers 39 (3) (1990)
Jien-Chung Lo, Suchai Thanawastien, T. R. N. Rao
Concurrent error detection in arithmetic and logical operations using Berger codes. IEEE Symposium on Computer Arithmetic (1989)
Jien-Chung Lo, Suchai Thanawastien
The design of fast totally self-checking Berger code checkers based on Berger code partitioning. FTCS (1988)