Tatsuo Ohtsuki

Publication Activity (10 Years)

Years Active: 1976-2012
Publications (10 Years): 0

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
Robust Secure Scan Design Against Scan-Based Differential Cryptanalysis. IEEE Trans. Very Large Scale Integr. Syst. 20 (1) (2012)
Youhei Tsukamoto, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa
A Fast Selector-Based Subtract-Multiplication Unit and Its Application to Butterfly Unit. IPSJ Trans. Syst. LSI Des. Methodol. 4 (2011)
Masashi Tawada, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa
Exact, Fast and Flexible L1 Cache Configuration Simulation for Embedded Systems. Inf. Media Technol. 6 (4) (2011)
Youhei Tsukamoto, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa
A Fast Selector-Based Subtract-Multiplication Unit and Its Application to Butterfly Unit. Inf. Media Technol. 6 (2) (2011)
Sho Tanaka, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa
A Fault-Secure High-Level Synthesis Algorithm for RDR Architectures. IPSJ Trans. Syst. LSI Des. Methodol. 4 (2011)
Ryuta Nara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
Scan Vulnerability in Elliptic Curve Cryptosystems. IPSJ Trans. Syst. LSI Des. Methodol. 4 (2011)
Masashi Tawada, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa
Exact, Fast and Flexible L1 Cache Configuration Simulation for Embedded Systems. IPSJ Trans. Syst. LSI Des. Methodol. 4 (2011)
Ryuta Nara, Kei Satoh, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa
Scan-Based Side-Channel Attack against RSA Cryptosystems Using Scan Signatures. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2010)
Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
Improved Launch for Higher TDF Coverage With Fewer Test Patterns. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (8) (2010)
Youhua Shi, Kenta Tokumitsu, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
VLSI implementation of a fast intra prediction algorithm for H.264/AVC encoding. APCCAS (2010)
Ryuta Nara, Hiroshi Atobe, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
State-dependent changeable scan architecture against scan-based side channel attacks. ISCAS (2010)
Akira Ohchi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
Performance-driven high-level synthesis with floorplan for GDR architectures and its evaluation. ISCAS (2010)
Youhei Tsukamoto, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa
A fast selector-based subtract-multiplication unit and its application to Radix-2 butterfly unit. APCCAS (2010)
Ryuta Nara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
Scan-based attack against elliptic curve cryptosystems. ASP-DAC (2010)
Seungju Lee, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa
BusMesh NoC: A novel NoC architecture comprised of bus-based connection and global mesh routers. APCCAS (2010)
Kazuyuki Tanimura, Ryuta Nara, Shunitsu Kohara, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
). IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (9) (2009)
Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
Design-for-secure-test for crypto cores. ITC (2009)
Akira Ohchi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2009)
Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
X-Handling for Current X-Tolerant Compactors with More Unknowns and Maximal Compaction. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2009)
Nobuaki Tojo, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
Exact and fast L1 cache simulation for embedded systems. ASP-DAC (2009)
Nobuaki Tojo, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
A Two-Level Cache Design Space Exploration System for Embedded Applications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2009)
Ryuta Nara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
A Scan-Based Attack Based on Discriminators for AES Cryptosystems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2009)
Nobuaki Tojo, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
An L1 Cache Design Space Exploration System for Embedded Applications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (6) (2009)
Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
GECOM: Test data compression combined with all unknown response masking. ASP-DAC (2008)
Akira Ohchi, Shunitsu Kohara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
Floorplan-Driven High-Level Synthesis for Distributed/Shared-Register Architectures. IPSJ Trans. Syst. LSI Des. Methodol. 1 (2008)
Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
A Unified Test Compression Technique for Scan Stimulus and Unknown Masking Data with No Test Loss. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2008)
Kazuyuki Tanimura, Ryuta Nara, Shunitsu Kohara, Kazunori Shimizu, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
). ASP-DAC (2008)
Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
Unknown response masking with minimized observable response loss and mask data. APCCAS (2008)
Akiyuki Nagashima, Yuta Imai, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
Dynamically reconfigurable architecture for multi-rate compatible regular LDPC decoding. APCCAS (2008)
Ryo Tamura, Masayuki Honma, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, Makoto Satoh
FIR filter design on Flexible Engine/Generic ALU array and its dedicated synthesis algorithm. APCCAS (2008)
Akira Ohchi, Shunitsu Kohara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
Floorplan-Driven High-Level Synthesis for Distributed/Shared-Register Architectures. Inf. Media Technol. 3 (4) (2008)
Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
A Secure Test Technique for Pipelined Advanced Encryption Standard. IEICE Trans. Inf. Syst. (3) (2008)
Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
Design for Secure Test - A Case Study on Pipelined Advanced Encryption Standard. ISCAS (2007)
Jumpei Uchida, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
A Fast Elliptic Curve Cryptosystem LSI Embedding Word-Based Montgomery Multiplier. IEICE Trans. Electron. (3) (2006)
Shunitsu Kohara, Naoki Tomono, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
An interface-circuit synthesis method with configurable processor core in IP-based SoC designs. ASP-DAC (2006)
Youhua Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki
FCSCAN: an efficient multiscan-based test compression technique for test cost reduction. ASP-DAC (2006)
Youhua Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki
Selective Low-Care Coding: A Means for Test Data Compression in Circuits with Multiple Scan Chains. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2006)
Hideki Kawazu, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
Sub-operation Parallelism Optimization in SIMD Processor Core Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2005)
Nozomu Togawa, Hideki Kawazu, Jumpei Uchida, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki
Sub-operation parallelism optimization in SIMD processor synthesis and its experimental evaluations. ISCAS (4) (2005)
Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, Shinji Kimura
Low Power Test Compression Technique for Designs with Multiple Scan Chain. Asian Test Symposium (2005)
Nozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki
A SIMD Instruction Set and Functional Unit Synthesis Algorithm with SIMD Operation Decomposition. IEICE Trans. Inf. Syst. (7) (2005)
Naoki Tomono, Shunitsu Kohara, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
A processor core synthesis system in IP-based SoC design. ASP-DAC (2005)
Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
A cosynthesis algorithm for application specific processors with heterogeneous datapaths. ASP-DAC (2004)
Youhua Shi, Shinji Kimura, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
Alternative Run-Length Coding through Scan Chain Reconfiguration for Joint Minimization of Test Data Volume and Power Consumption in Scan Test. Asian Test Symposium (2004)
Nozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki
Instruction set and functional unit synthesis for SIMD processor cores. ASP-DAC (2004)
Jumpei Uchida, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
A thread partitioning algorithm in low power high-level synthesis. ASP-DAC (2004)
Nozomu Togawa, Takao Totsuka, Tatsuhiko Wakui, Masao Yanagisawa, Tatsuo Ohtsuki
A Hardware/Software Cosynthesis System for Processor Cores with Content Addressable Memories. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (5) (2003)
Koichi Tachikake, Nozomu Togawa, Yuichiro Miyaoka, Jinku Choi, Masao Yanagisawa, Tatsuo Ohtsuki
A hardware/software partitioning algorithm for SIMD processor cores. ASP-DAC (2003)
Nozomu Togawa, Kyosuke Kasahara, Yuichiro Miyaoka, Jinku Choi, Masao Yanagisawa, Tatsuo Ohtsuki
A Retargetable Simulator Generator for DSP Processor Cores with Packed SIMD-type Instructions. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2003)
Nozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki
A Hardware/Software Partitioning Algorithm for Processor Cores with Packed SIMD-Type Instructions. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2003)
Youhua Shi, Zhe Zhang, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki
A Built-in Reseeding Technique for LFSR-Based Test Pattern Generation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2003)
Shinichi Noda, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
A High-Level Energy-Optimizing Algorithm for System VLSIs Based on Area/Time/Power Estimation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2002)
Yuichiro Miyaoka, Jinku Choi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
An algorithm of hardware unit generation for processor core synthesis with packed SIMD type instructions. APCCAS (1) (2002)
Shinichi Noda, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
High-Level Area/Delay/Power Estimation for Low Power System VLSIs with Gated Clocks. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2002)
Jinku Choi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
An Algorithm and a Flexible Architecture for Fast Block-Matching Motion Estimation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2002)
Jinku Choi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
VLSI Architecture for a Flexible Motion Estimation with Parameters. VLSI Design (2002)
Yuichiro Miyaoka, Yoshiharu Kataoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
Area/delay estimation for digital signal processor cores. ASP-DAC (2001)
Nozomu Togawa, Masayuki Ienaga, Masao Yanagisawa, Tatsuo Ohtsuki
An area/time optimizing algorithm in high-level synthesis for control-based hardwares (short paper). ASP-DAC (2000)
Nozomu Togawa, Kaoru Ukai, Masao Yanagisawa, Tatsuo Ohtsuki
A Simultaneous Placement and Global Routing Algorithm for FPGAs with Power Optimization. J. Circuits Syst. Comput. 9 (1-2) (1999)
Tingrong Zhao, Masao Yanagisawa, Tatsuo Ohtsuki
Fast Motion Estimation Scheme for Video Coding Using Feature Vector Matching and Motion Vector's Correlations. J. Circuits Syst. Comput. 9 (1-2) (1999)
Nozomu Togawa, Takashi Sakurai, Masao Yanagisawa, Tatsuo Ohtsuki
A Hardware/Software Partitioning Algorithm for Processor Cores of Digital Signal Processing. ASP-DAC (1999)
Nozomu Togawa, Takafumi Hisaki, Masao Yanagisawa, Tatsuo Ohtsuki
A High-Level Synthesis System for Digital Signal Processing Based on Enumerating Data-Flow Graphs. ASP-DAC (1998)
Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
Maple-opt: a performance-oriented simultaneous technology mapping, placement, and global routing algorithm for FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17 (9) (1998)
Nozomu Togawa, Kayoko Hagi, Masao Yanagisawa, Tatsuo Ohtsuki
An Incremental Placement and Global Routing Algorithm for Field-Programmable Gate Arrays. ASP-DAC (1998)
Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki
A simultaneous placement and global routing algorithm with path length constraints for transport-processing FPGAs. ASP-DAC (1997)
Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki
A Performance-Oriented Circuit Partitioning Algorithm with Logic-Block Replication for Multi-FPGA Systems. J. Circuits Syst. Comput. 7 (5) (1997)
Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki
Maple-opt: a simultaneous technology mapping, placement, and global routing algorithm FPGAs with performance optimization. ASP-DAC (1995)
Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki
A Simultaneous Placement and Global Routing Algorithm for FPGAs. ISCAS (1994)
Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki
A simultaneous technology mapping, placement, and global routing algorithm for field-programmable gate arrays. ICCAD (1994)
Toru Awashima, Wataru Yamamoto, Masao Sato, Tatsuo Ohtsuki
An optimal chip compaction method based on shortest path algorithm with automatic jog insertion. ICCAD (1992)
Masao Sato, Kazuto Kubota, Tatsuo Ohtsuki
A Hardware Implementation of Gridless Routing Based on Content Addressable Memory. DAC (1990)
Ernest S. Kuh, Tatsuo Ohtsuki
Recent advances in VLSI layout. Proc. IEEE 78 (2) (1990)
Masao Sato, Tatsuo Ohtsuki
Applications of computational geometry to VLSI layout pattern design. Integr. 5 (3-4) (1987)
Kei Suzuki, Yusuke Matsunaga, Masayoshi Tachibana, Tatsuo Ohtsuki
A Hardware Maze Router with Application to Interactive Rip-Up and Reroute. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 5 (4) (1986)
Tatsuo Ohtsuki, Hajimu Mori, Toshinobu Kashiwabara, Toshio Fujisawa
On Minimal Augmentation of a Graph to Obtain an Interval Graph. J. Comput. Syst. Sci. 22 (1) (1981)
Tatsuo Ohtsuki
The two disjoint path problem and wire routing design. Graph Theory and Algorithms (1980)
Tatsuo Ohtsuki, Hajimu Mori, Ernest S. Kuh, Toshinobu Kashiwabara, Toshio Fujisawa
One-dimensional logic gate assignment and interval graphs. COMPSAC (1979)
Tatsuo Ohtsuki
A Fast Algorithm for Finding an Optimal Ordering for Vertex Elimination on a Graph. SIAM J. Comput. 5 (1) (1976)