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A Hardware/Software Cosynthesis System for Processor Cores with Content Addressable Memories.
Nozomu Togawa
Takao Totsuka
Tatsuhiko Wakui
Masao Yanagisawa
Tatsuo Ohtsuki
Published in:
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2003)
Keyphrases
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content addressable
multi core processors
hardware software
hw sw
parallel programming
peer to peer
computing resources
processor core
multithreading
hardware and software
gene expression programming
cloud computing
computing systems
information systems
fault tolerance
operating system
response time
multimedia