Area/delay estimation for digital signal processor cores.

Yuichiro Miyaoka Yoshiharu Kataoka Nozomu Togawa Masao Yanagisawa Tatsuo Ohtsuki

Published in: ASP-DAC (2001)

Keyphrases

digital signal processor
multi core architecture
real time
texas instruments
maximum likelihood estimation
accurate estimation
estimation process
real time embedded
data sets
monte carlo simulation