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An algorithm of hardware unit generation for processor core synthesis with packed SIMD type instructions.

Yuichiro MiyaokaJinku ChoiNozomu TogawaMasao YanagisawaTatsuo Ohtsuki
Published in: APCCAS (1) (2002)
Keyphrases
  • learning algorithm
  • k means
  • low cost
  • parallel implementation
  • optimal solution
  • tree structure
  • processor core
  • web services
  • data processing