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Dynamically reconfigurable architecture for multi-rate compatible regular LDPC decoding.
Akiyuki Nagashima
Yuta Imai
Nozomu Togawa
Masao Yanagisawa
Tatsuo Ohtsuki
Published in:
APCCAS (2008)
Keyphrases
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ldpc codes
decoding algorithm
low density parity check
real time
management system
distributed source coding
distributed video coding
software architecture
rate allocation
turbo codes
network architecture
compressive sensing
image transmission
vlsi architecture