Ernest S. Kuh

Publication Activity (10 Years)

Years Active: 1979-2011
Publications (10 Years): 0

Publications

Ernest S. Kuh
Professor Ernest Kuh's talk. ISPD (2011)
Ling Zhang, Yulei Zhang, Akira Tsuchiya, Masanori Hashimoto, Ernest S. Kuh, Chung-Kuan Cheng
High performance on-chip differential signaling using passive compensation for global communication. ASP-DAC (2009)
Yulei Zhang, Ling Zhang, Alina Deutsch, George A. Katopis, Daniel M. Dreps, James F. Buckwalter, Ernest S. Kuh, Chung-Kuan Cheng
Design methodology of high performance on-chip global interconnect using terminated transmission-line. ISQED (2009)
Ling Zhang, Wenjian Yu, Yulei Zhang, Renshen Wang, Alina Deutsch, George A. Katopis, Daniel M. Dreps, James F. Buckwalter, Ernest S. Kuh, Chung-Kuan Cheng
Low Power Passive Equalizer Design for Computer Memory Links. Hot Interconnects (2008)
Rui Shi, Wenjian Yu, Yi Zhu, Chung-Kuan Cheng, Ernest S. Kuh
Efficient and accurate eye diagram prediction for high speed signaling. ICCAD (2008)
Ling Zhang, Wenjian Yu, Haikun Zhu, Alina Deutsch, George A. Katopis, Daniel M. Dreps, Ernest S. Kuh, Chung-Kuan Cheng
Low power passive equalizer optimization using tritonic step response. DAC (2008)
Zhengyong Zhu, He Peng, Chung-Kuan Cheng, Khosro Rouz, Manjit Borah, Ernest S. Kuh
Two-Stage Newton-Raphson Method for Transistor-Level Simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (5) (2007)
Zhengyong Zhu, Rui Shi, Chung-Kuan Cheng, Ernest S. Kuh
An unconditional stable general operator splitting method for transistor level transient analysis. ASP-DAC (2006)
Zhengyong Zhu, Khosro Rouz, Manjit Borah, Chung-Kuan Cheng, Ernest S. Kuh
Efficient transient simulation for transistor-level analysis. ASP-DAC (2005)
Qingjian Yu, Ernest S. Kuh
Accurate reduced RL model for frequency dependent transmission lines. ICECS (2002)
Qingjian Yu, Ernest S. Kuh
Explicit formulas and efficient algorithm for moment computation of coupled RC trees with lumped and distributed elements. DATE (2001)
Qingjian Yu, Ernest S. Kuh
New Efficient and Accurate Moment Matching Based Model for Crosstalk Estimation in Coupled RC Trees. ISQED (2001)
Qingjian Yu, Ernest S. Kuh
Moment computation of lumped and distributed coupled RC trees with application to delay and crosstalk estimation. Proc. IEEE 89 (5) (2001)
Qingjian Yu, Janet Meiling Wang, Ernest S. Kuh
Passive model order reduction algorithm based on Chebyshev expansion of impulse response of interconnect networks. DAC (2000)
Pinghong Chen, Ernest S. Kuh
Floorplan sizing by linear programming approximation. DAC (2000)
Janet Meiling Wang, Qingjian Yu, Ernest S. Kuh
Coupled Noise Estimation for Distributed RC Interconnect Model. DATE (1999)
Janet Meiling Wang, Ernest S. Kuh, Qingjian Yu
The Chebyshev expansion based passive model for distributed interconnect networks. ICCAD (1999)
Qingjian Yu, Janet Meiling Wang, Ernest S. Kuh
Multipoint moment matching model for multiport distributed interconnect networks. ICCAD (1998)
Dongsheng Wang, Ernest S. Kuh
A new general connectivity model and its applications to timing-driven Steiner tree routing. ICECS (1998)
Dongsheng Wang, Ernest S. Kuh
A Performance-Driven MCM Router with Special Consideration of Crosstalk Reduction. DATE (1998)
Hiroshi Murata, Ernest S. Kuh
Sequence-pair based placement method for hard/soft/pre-placed modules. ISPD (1998)
Ernest S. Kuh
Physical design: reminiscing and looking ahead. ISPD (1997)
Tianxiong Xue, Ernest S. Kuh, Dongsheng Wang
Post global routing crosstalk synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16 (12) (1997)
Premal Buch, Ernest S. Kuh
SYMPHONY: A Fast Mixed Signal Simulator for BiMOS Analog/Digital Circuits. VLSI Design (1997)
Henrik Esbensen, Ernest S. Kuh
A performance-driven IC/MCM placement algorithm featuring explicit design space exploration. ACM Trans. Design Autom. Electr. Syst. 2 (1) (1997)
Massoud Pedram, Narasimha B. Bhat, Ernest S. Kuh
Combining Technology Mapping With Layout. VLSI Design 5 (2) (1997)
Xianlong Hong, Tianxiong Xue, Jin Huang, Chung-Kuan Cheng, Ernest S. Kuh
TIGER: an efficient timing-driven global router for gate array and standard cell layout design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16 (11) (1997)
Henrik Esbensen, Ernest S. Kuh
EXPLORER: an interactive floorplanner for design space exploration. EURO-DAC (1996)
Dongsheng Wang, Ernest S. Kuh
Performance-Driven Interconnect Global Routing. Great Lakes Symposium on VLSI (1996)
Tianxiong Xue, Ernest S. Kuh, Dongsheng Wang
Post global routing crosstalk risk estimation and reduction. ICCAD (1996)
Qingjian Yu, Ernest S. Kuh, Tianxiong Xue
Moment models of general transmission lines with application to interconnect analysis and optimization. IEEE Trans. Very Large Scale Integr. Syst. 4 (4) (1996)
Jun-Fa Mao, Janet Meiling Wang, Ernest S. Kuh
Simulation and sensitivity analysis of transmission line circuits by the characteristics method. ICCAD (1996)
Premal Buch, Shen Lin, Vijay Nagasamy, Ernest S. Kuh
Techniques for fast circuit simulation applied to power estimation of CMOS circuits. ISLPD (1995)
Akira Onozawa, Kamal Chaudhary, Ernest S. Kuh
Performance driven spacing algorithms using attractive and repulsive constraints for submicron LSI's. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14 (6) (1995)
Tianxiong Xue, Ernest S. Kuh
Post routing performance optimization via multi-link insertion and non-uniform wiresizing. ICCAD (1995)
Tianxiong Xue, Ernest S. Kuh
Post routing performance optimization via tapered link insertion and wiresizing. EURO-DAC (1995)
Qingjian Yu, Ernest S. Kuh
Exact moment matching model of transmission lines and application to interconnect delay estimation. IEEE Trans. Very Large Scale Integr. Syst. 3 (2) (1995)
Shen Lin, Ernest S. Kuh, Malgorzata Marek-Sadowska
Stepwise equivalent conductance circuit simulation technique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12 (5) (1993)
Shen Lin, Ernest S. Kuh
Circuit simulation for large interconnected IC networks. VLSI (1993)
Jin Huang, Xianlong Hong, Chung-Kuan Cheng, Ernest S. Kuh
An Efficient Timing-Driven Global Routing Algorithm. DAC (1993)
Kamal Chaudhary, Akira Onozawa, Ernest S. Kuh
A spacing algorithm for performance enhancement and cross-talk reduction. ICCAD (1993)
Tianxiong Xue, Takashi Fujii, Ernest S. Kuh
A new performance-driven global routing algorithm for gate array. VLSI (1993)
Minshine Shih, Ernest S. Kuh
Quadratic Boolean Programming for Performance-Driven System Partitioning. DAC (1993)
Xianlong Hong, Tianxiong Xue, Ernest S. Kuh, Chung-Kuan Cheng, Jin Huang
Performance-Driven Steiner Tree Algorithm for Global Routing. DAC (1993)
Takashi Mitsuhashi, Ernest S. Kuh
Power and Ground Network Topology Optimization for Cell Based VLSIs. DAC (1992)
Shen Lin, Ernest S. Kuh
Transient Simulation of Lossy Interconnect. DAC (1992)
Shen Lin, Ernest S. Kuh, Malgorzata Marek-Sadowska
A New Accurate and Efficient Timing Simulator. VLSI Design (1992)
Xianlong Hong, Jin Huang, Chung-Kuan Cheng, Ernest S. Kuh
FARM: An Efficient Feed-Through Pin Assignment Algorithm. DAC (1992)
Minshine Shih, Ernest S. Kuh, Ren-Song Tsay
Performance-Driven System Partitioning on Multi-Chip Modules. DAC (1992)
Shen Lin, Ernest S. Kuh
Transient simulation of lossy coupled transmission lines. EURO-DAC (1992)
Shen Lin, Malgorzata Marek-Sadowska, Ernest S. Kuh
SWEC: a Step Wise Equivalent Conductance timing simulator for CMOS VLSI circuits. EURO-DAC (1991)
Arvind Srinivasan, Kamal Chaudhary, Ernest S. Kuh
RITUAL: Performance Driven Placement Algorithm for Small Cell ICs. ICCAD (1991)
Massoud Pedram, Kamal Chaudhary, Ernest S. Kuh
I/O Pad Assignment Based on the Circuit Structure. ICCD (1991)
Deborah C. Wang, Ernest S. Kuh
New Algorithms For Two- and Three-Layer Channel Routin. Int. J. Circuit Theory Appl. 19 (6) (1991)
Arvind Srinivasan, Ernest S. Kuh
MOLE: a sea-of-gates detailed router. EURO-DAC (1990)
Kwang-Ting Cheng, Vishwani D. Agrawal, Ernest S. Kuh
A Simulation-Based Method for Generating Tests for Sequential Circuits. IEEE Trans. Computers 39 (12) (1990)
Shen Lin, Malgorzata Marek-Sadowska, Ernest S. Kuh
Delay and Area Optimization in Standard-Cell Design. DAC (1990)
Xiao-Ming Xiong, Ernest S. Kuh
Geometric approach to VLSI layout compaction. Int. J. Circuit Theory Appl. 18 (4) (1990)
Ernest S. Kuh, Tatsuo Ohtsuki
Recent advances in VLSI layout. Proc. IEEE 78 (2) (1990)
Michael A. B. Jackson, Arvind Srinivasan, Ernest S. Kuh
Clock Routing for High-Performance ICs. DAC (1990)
Michael A. B. Jackson, Arvind Srinivasan, Ernest S. Kuh
A Fast Algorithm for Performance-Driven Placement. ICCAD (1990)
Massoud Pedram, Malgorzata Marek-Sadowska, Ernest S. Kuh
Floorplanning with Pin Assignment. ICCAD (1990)
Michael A. B. Jackson, Ernest S. Kuh
Performance-driven Placement of Cell Based IC's. DAC (1989)
Ren-Song Tsay, Ernest S. Kuh, Chi-Ping Hsu
PROUD: a sea-of-gates placement algorithm. IEEE Des. Test 5 (6) (1988)
Ren-Song Tsay, Ernest S. Kuh, Chi-Ping Hsu
Proud: A Fast Sea-of-Gates Placement Algorithm. DAC (1988)
Xiao-Ming Xiong, Ernest S. Kuh
The Constrained Via Minimization Problem for PCB and VLSI Design. DAC (1988)
Kwang-Ting Cheng, Vishwani D. Agrawal, Ernest S. Kuh
A sequential circuit test generation using threshold-value simulation. FTCS (1988)
Bernhard Eschermann, Wayne Wei-Ming Dai, Ernest S. Kuh, Massoud Pedram
Hierarchical placement for macrocells: a 'meet in the middle' approach. ICCAD (1988)
Wayne Wei-Ming Dai, Ernest S. Kuh
Simultaneous Floor Planning and Global Routing for Hierarchical Building-Block Layout. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6 (5) (1987)
Xiao-Ming Xiong, Ernest S. Kuh
Nutcracker: An Efficient and Intelligent Channel Spacer. DAC (1987)
Wayne Wei-Ming Dai, Masao Sato, Ernest S. Kuh
A Dynamic and Efficient Representation of Building-Block Layout. DAC (1987)
Howard H. Chen, Ernest S. Kuh
Glitter: A Gridless Variable-Width Channel Router. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 5 (4) (1986)
Wayne Wei-Ming Dai, Tetsuo Asano, Ernest S. Kuh
Routing Region Definition and Ordering Scheme for Building-Block Layout. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 4 (3) (1985)
Tom Tsan-Kuo Tarng, Malgorzata Marek-Sadowska, Ernest S. Kuh
An Efficient Single-Row Routing Algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 3 (3) (1984)
Chung-Kuan Cheng, Ernest S. Kuh
Module Placement Based on Resistive Network Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 3 (3) (1984)
Ernest S. Kuh
Editorial: Routing in Microelectronics. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2 (4) (1983)
Shuji Tsukiyama, Ernest S. Kuh, Isao Shirakawa
On the Layering Problem of Multilayer PWB Wiring. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2 (1) (1983)
Takeshi Yoshimura, Ernest S. Kuh
Efficient Algorithms for Channel Routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1 (1) (1982)
Shuji Tsukiyama, Ernest S. Kuh
Double-row planar routing and permutation layout. Networks 12 (3) (1982)
Shuji Tsukiyama, Ernest S. Kuh, Isao Shirakawa
On the layering problem of multilayer PWB wiring. DAC (1981)
Shuji Tsukiyama, Ernest S. Kuh, Isao Shirakawa
On the layering problem of multilayer PWB wiring. Graph Theory and Algorithms (1980)
Tatsuo Ohtsuki, Hajimu Mori, Ernest S. Kuh, Toshinobu Kashiwabara, Toshio Fujisawa
One-dimensional logic gate assignment and interval graphs. COMPSAC (1979)
Ernest S. Kuh
Single-row routing and extensions. COMPSAC (1979)