Daniel M. Dreps

Publication Activity (10 Years)

Years Active: 2007-2018
Publications (10 Years): 3

Top Topics

Memory Subsystem

Ibm Zenterprise

Top Venues

IBM J. Res. Dev.

Publications

Jeffrey Stuecheli, William J. Starke, John D. Irish, L. Baba Arimilli, Daniel M. Dreps, Bart Blaner, Curt Wollbrink, Brian Allison
IBM POWER9 opens up a new era of acceleration enablement: OpenCAPI. IBM J. Res. Dev. 62 (4/5) (2018)
Bharat Sukhwani, Thomas Roewer, Charles L. Haymes, Kyu-hyoun Kim, Adam J. McPadden, Daniel M. Dreps, Dean Sanner, Jan van Lunteren, Sameh W. Asaad
Contutto: a novel FPGA-based prototyping platform enabling innovation in the memory subsystem of a server class processor. MICRO (2017)
Victor V. Zyuban, Joshua Friedrich, Daniel M. Dreps, Jürgen Pille, Donald W. Plass, Phillip J. Restle, Zeynep Toprak Deniz, Matthew M. Ziegler, Sam G. Chu, Md. Saiful Islam, James D. Warnock, Bob Philhower, Rahul M. Rao, Gregory S. Still, David Shan, Eric Fluhr, Jose Paredes, Dieter F. Wendel, Christopher J. Gonzalez, D. Hogenmiller, Ruchir Puri, Scott A. Taylor, Stephen D. Posluszny
IBM POWER8 circuit design and energy optimization. IBM J. Res. Dev. 59 (1) (2015)
Joshua Friedrich, Hung Q. Le, William J. Starke, Jeff Stuecheli, Balaram Sinharoy, Eric J. Fluhr, Daniel M. Dreps, Victor V. Zyuban, Gregory S. Still, Christopher J. Gonzalez, David Hogenmiller, Frank Malgioglio, Ryan Nett, Ruchir Puri, Phillip J. Restle, David Shan, Zeynep Toprak Deniz, Dieter F. Wendel, Matthew M. Ziegler, Dave W. Victor
processor: Designed for big data, analytics, and cloud environments. ICICDT (2014)
Eric J. Fluhr, Joshua Friedrich, Daniel M. Dreps, Victor V. Zyuban, Gregory S. Still, Christopher J. Gonzalez, Allen Hall, David Hogenmiller, Frank Malgioglio, Ryan Nett, Jose Paredes, Juergen Pille, Donald W. Plass, Ruchir Puri, Phillip J. Restle, David Shan, Kevin Stawiasz, Zeynep Toprak Deniz, Dieter F. Wendel, Matthew M. Ziegler
: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth. ISSCC (2014)
Rohan Mandrekar, Yaping Zhou, Sungjun Chun, Anand Haridass, Jinwoo Choi, Nanju Na, Daniel M. Dreps, Roger D. Weekly, Paul Harvey
Channel Optimization for the Design of High Speed I/O links. VLSI Design (2010)
Yulei Zhang, Ling Zhang, Alina Deutsch, George A. Katopis, Daniel M. Dreps, James F. Buckwalter, Ernest S. Kuh, Chung-Kuan Cheng
Design methodology of high performance on-chip global interconnect using terminated transmission-line. ISQED (2009)
Thomas-Michael Winkel, Hubert Harrer, Dierk Kaller, Jochen Supper, Daniel M. Dreps, Kenneth L. Christian, D. Cosmadelis, Tingdong Zhou, Thomas Strach, J. Ludwig, David L. Edwards
Packaging design challenges of the IBM System z10 Enterprise Class server. IBM J. Res. Dev. 53 (1) (2009)
Kyu-hyoun Kim, Daniel M. Dreps, Frank D. Ferraiolo, Paul W. Coteus, Seongwon Kim, Sergey V. Rylov, Daniel J. Friedman
0.48psrms-jitter 0.8-to-5GHz non-PLL/DLL all-digital phase generator/rotator in 45nm SOI CMOS. ISSCC (2009)
Kyu-hyoun Kim, Paul W. Coteus, Daniel M. Dreps, Seongwon Kim, Sergey V. Rylov, Daniel J. Friedman
A 2.6mW 370MHz-to-2.5GHz Open-Loop Quadrature Clock Generator. ISSCC (2008)
Ling Zhang, Wenjian Yu, Yulei Zhang, Renshen Wang, Alina Deutsch, George A. Katopis, Daniel M. Dreps, James F. Buckwalter, Ernest S. Kuh, Chung-Kuan Cheng
Low Power Passive Equalizer Design for Computer Memory Links. Hot Interconnects (2008)
Ling Zhang, Wenjian Yu, Haikun Zhu, Alina Deutsch, George A. Katopis, Daniel M. Dreps, Ernest S. Kuh, Chung-Kuan Cheng
Low power passive equalizer optimization using tritonic step response. DAC (2008)
Hubert Harrer, Daniel M. Dreps, Thomas-Michael Winkel, Wolfgang Scholz, Bao G. Truong, Andreas Huber, Tingdong Zhou, Kenneth L. Christian, Gary F. Goth
High-speed interconnect and packaging design of the IBM System z9 processor cage. IBM J. Res. Dev. 51 (1/2) (2007)