Kyu-hyoun Kim

Publication Activity (10 Years)

Years Active: 2006-2020
Publications (10 Years): 3

Top Topics

Ibm Zenterprise

Memory Subsystem

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Saravanan Sethuraman, Venkata Kalyan Tavva, Karthick Rajamani, Chitra K. Subramanian, Kyu-hyoun Kim, Hillery C. Hunter, M. B. Srinivas
Temperature Aware Adaptations for Improved Read Reliability in STT-MRAM Memory Subsystem. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (12) (2020)
Seokin Hong, Prashant Jayaprakash Nair, Bülent Abali, Alper Buyuktosunoglu, Kyu-hyoun Kim, Michael B. Healy
Attaché: Towards Ideal Memory Compression by Mitigating Metadata Bandwidth Overheads. MICRO (2018)
Bharat Sukhwani, Thomas Roewer, Charles L. Haymes, Kyu-hyoun Kim, Adam J. McPadden, Daniel M. Dreps, Dean Sanner, Jan van Lunteren, Sameh W. Asaad
Contutto: a novel FPGA-based prototyping platform enabling innovation in the memory subsystem of a server class processor. MICRO (2017)
Janani Mukundan, Hillery C. Hunter, Kyu-hyoun Kim, Jeffrey Stuecheli, José F. Martínez
Understanding and mitigating refresh overheads in high-density DDR4 DRAM systems. ISCA (2013)
Kyu-hyoun Kim, Daniel M. Dreps, Frank D. Ferraiolo, Paul W. Coteus, Seongwon Kim, Sergey V. Rylov, Daniel J. Friedman
0.48psrms-jitter 0.8-to-5GHz non-PLL/DLL all-digital phase generator/rotator in 45nm SOI CMOS. ISSCC (2009)
Kyu-hyoun Kim, Paul W. Coteus, Daniel M. Dreps, Seongwon Kim, Sergey V. Rylov, Daniel J. Friedman
A 2.6mW 370MHz-to-2.5GHz Open-Loop Quadrature Clock Generator. ISSCC (2008)
Kyu-hyoun Kim, Hoeju Chung, Woo-Seop Kim, Moon-Sook Park, Young-Chan Jang, Jinyoung Kim, Hwan-Wook Park, Uksong Kang, Paul W. Coteus, Joo-Sun Choi, Changhyun Kim
An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I/O Error Detection Scheme. IEEE J. Solid State Circuits 42 (1) (2007)
Kyu-hyoun Kim, In-Young Chung
A Second Order Mixed-Mode Charge Pump Scheme for Low Phase/Duty Error and Low Power Consumption. IEICE Trans. Electron. (1) (2007)
Kyu-hyoun Kim, Uksong Kang, Hoeju Chung, Dukha Park, Woo-Seop Kim, Young-Chan Jang, Moon-Sook Park, Hoon Lee, Jinyoung Kim, Jung Sunwoo, Hwan-Wook Park, Hyun-Kyung Kim, Su-Jin Chung, Jae-Kwan Kim, Hyung-Seuk Kim, Kee-Won Kwon, Young-Taek Lee, Joo-Sun Choi, Changhyun Kim
An 8Gb/s/pin 9.6ns Row-Cycle 288Mb Deca-Data Rate SDRAM with an I/O Error-Detection Scheme. ISSCC (2006)
Kyu-hyoun Kim, Young-Soo Sohn, Chan-Kyoung Kim, Moon-Sook Park, Dong-Jin Lee, Woo-Seop Kim, Changhyun Kim
A 20-gb/s 256-mb DRAM with an inductorless quadrature PLL and a cascaded pre-emphasis transmitter. IEEE J. Solid State Circuits 41 (1) (2006)