An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I/O Error Detection Scheme.
Kyu-hyoun KimHoeju ChungWoo-Seop KimMoon-Sook ParkYoung-Chan JangJinyoung KimHwan-Wook ParkUksong KangPaul W. CoteusJoo-Sun ChoiChanghyun KimPublished in: IEEE J. Solid State Circuits (2007)
Keyphrases
- data sets
- detection scheme
- data transfer
- data collection
- storage systems
- input output
- data structure
- statistical analysis
- data processing
- data sources
- prior knowledge
- data analysis
- end users
- high quality
- image data
- database
- original data
- training data
- data quality
- raw data
- network structure
- error rate
- data distribution
- spatial data
- motion vectors
- synthetic data
- input data
- data points
- probability distribution
- computational complexity