Young-Chan Jang

Publication Activity (10 Years)

Years Active: 2006-2024
Publications (10 Years): 21

Top Topics

Delta Sigma Modulators

Analog To Digital Converter

Radially Symmetric

Top Venues

IEICE Trans. Electron.

IEEE Trans. Consumer Electron.

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Changmin Song, Hoyong Jung, KyoungSeop Chang, Kwanglae Cho, Seungyong Yoon, Young-Chan Jang
A 24-Gb/s MIPI C-/D-PHY Receiver Bridge Chip With Phase Error Calibration Supporting FPGA-Based Frame Grabber. IEEE Trans. Very Large Scale Integr. Syst. 32 (4) (2024)
Sihan Kim, Changmin Song, Jinseok Kim, Yonghun Oh, Changwan Kim, Young-Chan Jang
A 10-Gb/s Dual-Loop Reference-less CDR with FD Controller. ISOCC (2023)
Haewoon Son, WonSeok Yang, Hoyong Jung, Young-Chan Jang
1-kS/s 12-bit SAR ADC with Burst Conversion. ISOCC (2023)
Hye-Min Shin, Hae-Won Son, Tai-Soon Park, Tae-Woo Oh, Young-Chan Jang
First-order Continuous Time Delta-sigma Modulator with 3-bit SAR ADC and PNM DAC. ISOCC (2023)
Changmin Song, Minjun Cho, Sihan Kim, Young-Chan Jang
4.5 Gsymbol/s/lane MIPI C-PHY Receiver with Channel Mismatch Calibration. ISCAS (2023)
Wonkyu Do, Neungin Jeon, Hoyong Jung, Young-Chan Jang
Second-order Incremental Delta-sigma Modulator with 3-bit SAR ADC and Capacitor Sharing Scheme. ISOCC (2022)
Changmin Song, Se-Hyeon Cho, Young-Chan Jang
A 0.2 ‒ 1.2GHz Adaptive Bandwidth PLL with Controllable KVCO. ISOCC (2021)
Hoyong Jung, Neungin Jeon, Young-Chan Jang
Second-order Noise Shaping SAR ADC using 3-input Comparator with Voltage Gain Calibration. ISOCC (2021)
Seokwon Choi, Changmin Song, Young-Chan Jang
A 3.0 Gsymbol/s/lane MIPI C-PHY Receiver with Adaptive Level-Dependent Equalizer for Mobile CMOS Image Sensor. Sensors 21 (15) (2021)
Pil-Ho Lee, Young-Chan Jang
A 6.84 Gbps/lane MIPI C-PHY Transceiver Bridge Chip With Level-Dependent Equalization. IEEE Trans. Circuits Syst. (11) (2020)
Pil-Ho Lee, Young-Chan Jang
A 20-Gb/s Receiver Bridge Chip With Auto-Skew Calibration for MIPI D-PHY Interface. IEEE Trans. Consumer Electron. 65 (4) (2019)
Jisu Son, Young-Chan Jang
A 10-bit 10-MS/s single-ended asynchronous SAR ADC with CDAC boosting common-mode voltage and controlling input voltage range. IEICE Electron. Express 16 (22) (2019)
Pil-Ho Lee, Young-Chan Jang
A 3Gbps/Lane MIPI D-PHY Transmission Buffer Chip. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (6) (2019)
Eunji Youn, Young-Chan Jang
12-bit 20M-S/s SAR ADC using C-R DAC and Capacitor Calibration. ISOCC (2018)
Ho-Seong Kim, Pil-Ho Lee, Jin-Wook Han, Seung-Hun Shin, Seung-Wuk Baek, Doo-Ill Park, Yongkyu Seo, Young-Chan Jang
A 10 Gbps D-PHY Transmitter Bridge Chip for FPGA-Based Frame Generator Supporting MIPI DSI of Mobile Display. IEICE Trans. Electron. (11) (2017)
Pil-Ho Lee, Han-Yeol Lee, Yeong-Woong Kim, Han-Young Hong, Young-Chan Jang
A 10-Gbps receiver bridge chip with deserializer for FPGA-based frame grabber supporting MIPI CSI-2. IEEE Trans. Consumer Electron. 63 (3) (2017)
Seung-Hun Shin, Pil-Ho Lee, Jin-Woo Park, Yu-Jeong Hwang, Young-Chan Jang
0.5 kHz-32 MHz digital fractional-N frequency synthesizer with burst-frequency switch. ISCAS (2017)
Jin-Wook Han, Pil-Ho Lee, Yeong-Woong Kim, Sang-Dong Kim, Jin-Woo Park, Young-Chan Jang
A clock recovery for 2.56 GSymbol/s MIPI C-PHY receiver. ISOCC (2017)
Pil-Ho Lee, Han-Yeol Lee, Hyun Bae Lee, Young-Chan Jang
An On-Chip Monitoring Circuit for Signal-Integrity Analysis of 8-Gb/s Chip-to-Chip Interfaces With Source-Synchronous Clock. IEEE Trans. Very Large Scale Integr. Syst. 25 (4) (2017)
Sang-Min Park, Yeon-Ho Jeong, Yu-Jeong Hwang, Pil-Ho Lee, Yeong-Woong Kim, Jisu Son, Han-Yeol Lee, Young-Chan Jang
A 10-bit 20-MS/s Asynchronous SAR ADC with Meta-Stability Detector Using Replica Comparators. IEICE Trans. Electron. (6) (2016)
Pil-Ho Lee, Yu-Jeong Hwang, Han-Yeol Lee, Hyun Bae Lee, Young-Chan Jang
An On-Chip Monitoring Circuit with 51-Phase PLL-Based Frequency Synthesizer for 8-Gb/s ODR Single-Ended Signaling Integrity Analysis. IEICE Trans. Electron. (4) (2016)
Pil-Ho Lee, Hyun Bae Lee, Young-Chan Jang
A 125MHz 64-Phase Delay-Locked Loop with Coarse-Locking Circuit Independent of Duty Cycle. IEICE Trans. Electron. (5) (2014)
Kwang-Hun Lee, Young-Chan Jang
A 2-Gb/s CMOS SLVS Transmitter with Asymmetric Impedance Calibration for Mobile Interfaces. IEICE Trans. Electron. (8) (2014)
Mungyu Kim, Hoon-Ju Chung, Young-Chan Jang
A 10-bit CMOS Digital-to-Analog Converter with Compact Size for Display Applications. IEICE Trans. Electron. (6) (2014)
Ji-Hun Eo, Yeon-Ho Jeong, Young-Chan Jang
An 8-Bit 100-kS/s CMOS Single-Ended SA ADC for 8×8 Point EEG/MEG Acquisition System. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2013)
Kwang-Hun Lee, Young-Chan Jang
A 1.8 V 0.18-μm 1 GHz CMOS Fast-Lock Phase-Locked Loop using a Frequency-to-Digital Converter. J. Inform. and Commun. Convergence Engineering 10 (2) (2012)
Hyun Bae Lee, Young-Chan Jang
Mirrored Serpentine Microstrip Lines for Reduction of Far-End Crosstalk. IEICE Trans. Electron. (6) (2012)
Ji-Hun Eo, Sang-Hun Kim, Mungyu Kim, Young-Chan Jang
A 1.8 V 40-MS/sec 10-bit 0.18-㎛ CMOS Pipelined ADC using a Bootstrapped Switch with Constant Resistance. J. Inform. and Commun. Convergence Engineering 10 (1) (2012)
Han-Yeol Lee, Young-Chan Jang
A true single-phase clocked flip-flop with leakage current compensation. IEICE Electron. Express 9 (23) (2012)
Ji-Hun Eo, Sang-Hun Kim, Young-Chan Jang
A 1 V 200 kS/s 10-bit Successive Approximation ADC for a Sensor Interface. IEICE Trans. Electron. (11) (2011)
Sang-Hun Kim, Yong-Hwan Lee, Hoon-Ju Chung, Young-Chan Jang
A Bootstrapped Analog Switch with Constant On-Resistance. IEICE Trans. Electron. (6) (2011)
Young-Chan Jang
A Self-Calibrating Per-Pin Phase Adjuster for Source Synchronous Double Data Rate Signaling in Parallel Interface. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2011)
Young-Chan Jang
A Swing Level Controlled Transmitter for Single-Ended Signaling with Center-Tapped Termination. IEICE Trans. Electron. (6) (2010)
Young-Chan Jang
An unmatched source synchronous I/O link for jitter reduction in a multi-phase clock system. IEICE Electron. Express 7 (11) (2010)
Young-Chan Jang
A digital phase corrector with a duty cycle detector and transmitter for a Quad Data Rate I/O scheme. IEICE Electron. Express 7 (3) (2010)
Young-Chan Jang, Hoeju Chung, Youngdon Choi, Hwan-Wook Park, Jaekwan Kim, Soouk Lim, Jung Sunwoo, Moon-Sook Park, Hyung-Seuk Kim, Sang-Yun Kim, Yun-Sang Lee, Woo-Seop Kim, Jung-Bae Lee, Jei-Hwan Yoo, Changhyun Kim
BER Measurement of a 5.8-Gb/s/pin Unidirectional Differential I/O for DRAM Application With DIMM Channel. IEEE J. Solid State Circuits 44 (11) (2009)
Young-Chan Jang, Jun-Hyun Bae, Sang-Hune Park, Jae-Yoon Sim, Hong-June Park
An 8.8-GS/s 6-bit CMOS Time-Interleaved Flash Analog-to-Digital Converter with Multi-Phase Clock Generator. IEICE Trans. Electron. (6) (2007)
Kyu-hyoun Kim, Hoeju Chung, Woo-Seop Kim, Moon-Sook Park, Young-Chan Jang, Jinyoung Kim, Hwan-Wook Park, Uksong Kang, Paul W. Coteus, Joo-Sun Choi, Changhyun Kim
An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I/O Error Detection Scheme. IEEE J. Solid State Circuits 42 (1) (2007)
Kyu-hyoun Kim, Uksong Kang, Hoeju Chung, Dukha Park, Woo-Seop Kim, Young-Chan Jang, Moon-Sook Park, Hoon Lee, Jinyoung Kim, Jung Sunwoo, Hwan-Wook Park, Hyun-Kyung Kim, Su-Jin Chung, Jae-Kwan Kim, Hyung-Seuk Kim, Kee-Won Kwon, Young-Taek Lee, Joo-Sun Choi, Changhyun Kim
An 8Gb/s/pin 9.6ns Row-Cycle 288Mb Deca-Data Rate SDRAM with an I/O Error-Detection Scheme. ISSCC (2006)
Young-Chan Jang, Jun-Hyun Bae, Hong-June Park
A Digital CMOS PWCL With Fixed-Delay Rising Edge and Digital Stability Control. IEEE Trans. Circuits Syst. II Express Briefs (10) (2006)