A 3Gbps/Lane MIPI D-PHY Transmission Buffer Chip.

Pil-Ho Lee Young-Chan Jang

Published in: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2019)

Keyphrases

low cost
high speed
analog vlsi
data transmission
high density
traffic flow
detection algorithm
circuit design
buffer size
memory access
physical design
vlsi implementation
single chip
chip design
variable bit rate
lane detection
random access memory
lane departure
dynamic range