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A 10-Gbps receiver bridge chip with deserializer for FPGA-based frame grabber supporting MIPI CSI-2.

Pil-Ho LeeHan-Yeol LeeYeong-Woong KimHan-Young HongYoung-Chan Jang
Published in: IEEE Trans. Consumer Electron. (2017)
Keyphrases
  • low cost
  • high speed
  • analog vlsi
  • high density
  • vlsi implementation
  • bayesian networks
  • key frames
  • conditional independence
  • physical design