An 8Gb/s/pin 9.6ns Row-Cycle 288Mb Deca-Data Rate SDRAM with an I/O Error-Detection Scheme.
Kyu-hyoun KimUksong KangHoeju ChungDukha ParkWoo-Seop KimYoung-Chan JangMoon-Sook ParkHoon LeeJinyoung KimJung SunwooHwan-Wook ParkHyun-Kyung KimSu-Jin ChungJae-Kwan KimHyung-Seuk KimKee-Won KwonYoung-Taek LeeJoo-Sun ChoiChanghyun KimPublished in: ISSCC (2006)
Keyphrases
- data sets
- detection scheme
- data distribution
- data structure
- data processing
- raw data
- high quality
- data analysis
- input data
- computer systems
- error rate
- high dimensional data
- data collection
- data points
- knowledge discovery
- training data
- original data
- data transfer
- statistical analysis
- xml documents
- missing data
- spatial data
- input output
- learning algorithm
- data quality
- databases