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A 1.8 V 0.18-μm 1 GHz CMOS Fast-Lock Phase-Locked Loop using a Frequency-to-Digital Converter.
Kwang-Hun Lee
Young-Chan Jang
Published in:
J. Inform. and Commun. Convergence Engineering (2012)
Keyphrases
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phase locked loop
high voltage
high speed
multipath
low voltage
analog vlsi
power consumption
low cost
low power
operating conditions
web services
multiscale
control method
circuit design