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A 125MHz 64-Phase Delay-Locked Loop with Coarse-Locking Circuit Independent of Duty Cycle.
Pil-Ho Lee
Hyun Bae Lee
Young-Chan Jang
Published in:
IEICE Trans. Electron. (2014)
Keyphrases
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duty cycle
clock frequency
power consumption
real time
high speed
database systems
parallel computing
multiresolution
field programmable gate array
parallel architecture
concurrency control
cmos technology
massively parallel
scheduling problem
high end