Jeffrey Stuecheli

Publication Activity (10 Years)

Years Active: 2009-2021
Publications (10 Years): 4

Top Topics

Energy Efficiency

Memory Subsystem

Ibm Power Processor

Top Venues

IBM J. Res. Dev.

Publications

Brian W. Thompto, Dung Q. Nguyen, José E. Moreira, Ramon Bertran, Hans M. Jacobson, Richard J. Eickemeyer, Rahul M. Rao, Michael Goulet, Marcy Byers, Christopher J. Gonzalez, Karthik Swaminathan, Nagu R. Dhanwada, Silvia M. Müller, Andreas Wagner, Satish Kumar Sadasivam, Robert K. Montoye, William J. Starke, Christian G. Zoellin, Michael S. Floyd, Jeffrey Stuecheli, Nandhini Chandramoorthy, John-David Wellman, Alper Buyuktosunoglu, Matthias Pflanz, Balaram Sinharoy, Pradip Bose
Energy Efficiency Boost in the AI-Infused POWER10 Processor. ISCA (2021)
William J. Starke, Brian W. Thompto, Jeffrey Stuecheli, José E. Moreira
IBM's POWER10 Processor. IEEE Micro 41 (2) (2021)
Jeffrey Stuecheli, William J. Starke, John D. Irish, L. Baba Arimilli, Daniel M. Dreps, Bart Blaner, Curt Wollbrink, Brian Allison
IBM POWER9 opens up a new era of acceleration enablement: OpenCAPI. IBM J. Res. Dev. 62 (4/5) (2018)
William J. Starke, J. S. Dodson, Jeffrey Stuecheli, Eric Retter, Brad W. Michael, Stephen J. Powell, James A. Marcella
IBM POWER9 memory architectures for optimized systems. IBM J. Res. Dev. 62 (4/5) (2018)
Jeffrey Stuecheli, Bart Blaner, C. R. Johns, M. S. Siegel
CAPI: A Coherent Accelerator Processor Interface. IBM J. Res. Dev. 59 (1) (2015)
Balaram Sinharoy, Randal C. Swanberg, Naresh Nayar, Bruce G. Mealey, Jeffrey Stuecheli, Berni Schiefer, Jens Leenstra, J. Jann, P. Oehler, D. Levitan, S. Eisen, D. Sanner, Thomas Pflueger, Cédric Lichtenau, W. E. Hall, T. Block
Advanced features in IBM POWER8 systems. IBM J. Res. Dev. 59 (1) (2015)
William J. Starke, Jeffrey Stuecheli, David Daly, J. S. Dodson, Florian Auernhammer, Patricia Sagmeister, Guy L. Guthrie, Charles F. Marino, M. S. Siegel, Bart Blaner
The cache and memory subsystems of the IBM POWER8 processor. IBM J. Res. Dev. 59 (1) (2015)
Janani Mukundan, Hillery C. Hunter, Kyu-hyoun Kim, Jeffrey Stuecheli, José F. Martínez
Understanding and mitigating refresh overheads in high-density DDR4 DRAM systems. ISCA (2013)
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly, Hillery C. Hunter, Lizy K. John
Coordinating DRAM and Last-Level-Cache Policies with the Virtual Write Queue. IEEE Micro 31 (1) (2011)
Dimitris Kaseridis, Jeffrey Stuecheli, Lizy Kurian John
Minimalist open-page: a DRAM page-mode scheduling policy for the many-core era. MICRO (2011)
Dimitris Kaseridis, Muhammad Faisal Iqbal, Jeffrey Stuecheli, Lizy Kurian John
MCFQ: Leveraging Memory-level Parallelism and Application's Cache Friendliness for Efficient Management of Quasi-partitioned Last-level Caches. PACT (2011)
Jeffrey Stuecheli, Dimitris Kaseridis, Hillery C. Hunter, Lizy K. John
Elastic Refresh: Techniques to Mitigate Refresh Penalties in High Density Memory. MICRO (2010)
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly, Hillery C. Hunter, Lizy K. John
The virtual write queue: coordinating DRAM and last-level cache policies. ISCA (2010)
Dimitris Kaseridis, Jeffrey Stuecheli, Jian Chen, Lizy Kurian John
A bandwidth-aware memory-subsystem resource management using non-invasive resource profilers for large CMP systems. HPCA (2010)
Dimitris Kaseridis, Jeffrey Stuecheli, Lizy K. John
Bank-aware Dynamic Cache Partitioning for Multicore Architectures. ICPP (2009)