Phillip J. Restle

Publication Activity (10 Years)

Years Active: 1997-2023
Publications (10 Years): 10

Top Topics

Functional Verification

Ibm Power Processor

Top Venues

IEEE J. Solid State Circuits

Publications

Brian T. Vanderpool, Phillip J. Restle, Eric Fluhr, Gregory S. Still, Francesco A. Campisano, Ian Charmichael, Eric Marz, Rahul Batra, Richard L. Willaman
Deterministic Frequency and Voltage Enhancements on the POWER10 Processor. IEEE J. Solid State Circuits 58 (1) (2023)
Brian T. Vanderpool, Phillip J. Restle, Eric J. Fluhr, Gregory S. Still, Frank Campisano, Ian Carmichael, Eric Marz, Rahul Batra, Richard L. Willaman
Processor. ISSCC (2022)
Christopher J. Berry, David Wolpert, Christos Vezyrtzis, Richard F. Rizzolo, Sean M. Carey, Yaniv Maroz, Hunter F. Shi, Dureseti Chidambarrao, Christian Jacobi, Anthony Saporito, Thomas Strach, Alper Buyuktosunoglu, Preetham Lobo, Pierce Chuang, Pawel Owczarczyk, Ramon Bertran, Tobias Webel, Phillip J. Restle
IBM z14: Processor Characterization and Power Management for High-Reliability Mainframe Systems. IEEE J. Solid State Circuits 54 (1) (2019)
Christos Vezyrtzis, Thomas Strach, Pierce I-Jen Chuang, Preetham Lobo, Richard F. Rizzolo, Tobias Webel, Pawel Owczarczyk, Alper Buyuktosunoglu, Ramon Bertran, David T. Hui, Susan M. Eickhoff, Michael S. Floyd, Gerard Salem, Sean M. Carey, Stelios G. Tsapepas, Phillip J. Restle
Droop mitigation using critical-path sensors and an on-chip distributed power supply estimation engine in the z14™ enterprise processor. ISSCC (2018)
Phillip J. Restle, Kostas Doris, Vivek De, Paul Ferguson
EE5: Lessons learned - Great circuits that didn't work - (Oops, if only i had known!). ISSCC (2018)
Christopher J. Gonzalez, Michael S. Floyd, Eric Fluhr, Phillip J. Restle, Daniel Dreps, Michael A. Sperling, Rahul M. Rao, David Hogenmiller, Christos Vezyrtzis, Pierce Chuang, Daniel Lewis, Ricardo Escobar, Vinod Ramadurai, Ryan Kruse, Juergen Pille, Ryan Nett, Pawel Owczarczyk, Joshua Friedrich, Jose Paredes, Timothy Diemoz, Md. Saiful Islam, Donald W. Plass, Paul Muench
The 24-Core POWER9 Processor With Adaptive Clocking, 25-Gb/s Accelerator Links, and 16-Gb/s PCIe Gen4. IEEE J. Solid State Circuits 53 (1) (2018)
Youngmin Shin, Phillip J. Restle, Edith Beigné
Session 7 overview: Neuromorphic, clocking and security circuits: Digital circuits subcommittee. ISSCC (2018)
Michael S. Floyd, Phillip J. Restle, Michael A. Sperling, Pawel Owczarczyk, Eric J. Fluhr, Joshua Friedrich, Paul Muench, Timothy Diemoz, Pierce Chuang, Christos Vezyrtzis
26.5 Adaptive clocking in the POWER9™ processor for voltage droop protection. ISSCC (2017)
Pierce I-Jen Chuang, Christos Vezyrtzis, Divya Pathak, Richard F. Rizzolo, Tobias Webel, Thomas Strach, Otto A. Torreiter, Preetham Lobo, Alper Buyuktosunoglu, Ramon Bertran, Michael S. Floyd, Malcolm S. Ware, Gerard Salem, Sean M. Carey, Phillip J. Restle
26.2 Power supply noise in a 22nm z13™ microprocessor. ISSCC (2017)
Michael Scheuermann, Shurong Tian, Raphael Robertazzi, Matthew R. Wordeman, C. Bergeron, H. Jacobson, Phillip J. Restle, Joel Silberman, Christy Tyberg
Thermal analysis of multi-layer functional 3D logic stacks. 3DIC (2016)
David Shan, Phillip J. Restle, Doug Malone, Robert A. Groves, Eric Lai, Michael Koch, Jason Hibbeler, Yong Kim, Christos Vezyrtzis, Jan Feder, David Hogenmiller, Thomas J. Bucelot
. VLSIC (2015)
Eric J. Fluhr, Steve Baumgartner, David W. Boerstler, John F. Bulzacchelli, Timothy Diemoz, Daniel Dreps, George English, Joshua Friedrich, Anne Gattiker, Tilman Gloekler, Christopher J. Gonzalez, Jason Hibbeler, Keith A. Jenkins, Yong Kim, Paul Muench, Ryan Nett, Jose Paredes, Juergen Pille, Donald W. Plass, Phillip J. Restle, Raphael Robertazzi, David Shan, David W. Siljenberg, Michael A. Sperling, Kevin Stawiasz, Gregory S. Still, Zeynep Toprak Deniz, James D. Warnock, Glen A. Wiedemeier, Victor V. Zyuban
The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking. IEEE J. Solid State Circuits 50 (1) (2015)
Victor V. Zyuban, Joshua Friedrich, Daniel M. Dreps, Jürgen Pille, Donald W. Plass, Phillip J. Restle, Zeynep Toprak Deniz, Matthew M. Ziegler, Sam G. Chu, Md. Saiful Islam, James D. Warnock, Bob Philhower, Rahul M. Rao, Gregory S. Still, David Shan, Eric Fluhr, Jose Paredes, Dieter F. Wendel, Christopher J. Gonzalez, D. Hogenmiller, Ruchir Puri, Scott A. Taylor, Stephen D. Posluszny
IBM POWER8 circuit design and energy optimization. IBM J. Res. Dev. 59 (1) (2015)
Phillip J. Restle, David Shan, David Hogenmiller, Yong Kim, Alan J. Drake, Jason Hibbeler, Thomas J. Bucelot, Gregory S. Still, Keith A. Jenkins, Joshua Friedrich
microprocessor. ISSCC (2014)
Joshua Friedrich, Hung Q. Le, William J. Starke, Jeff Stuecheli, Balaram Sinharoy, Eric J. Fluhr, Daniel M. Dreps, Victor V. Zyuban, Gregory S. Still, Christopher J. Gonzalez, David Hogenmiller, Frank Malgioglio, Ryan Nett, Ruchir Puri, Phillip J. Restle, David Shan, Zeynep Toprak Deniz, Dieter F. Wendel, Matthew M. Ziegler, Dave W. Victor
processor: Designed for big data, analytics, and cloud environments. ICICDT (2014)
Eric J. Fluhr, Joshua Friedrich, Daniel M. Dreps, Victor V. Zyuban, Gregory S. Still, Christopher J. Gonzalez, Allen Hall, David Hogenmiller, Frank Malgioglio, Ryan Nett, Jose Paredes, Juergen Pille, Donald W. Plass, Ruchir Puri, Phillip J. Restle, David Shan, Kevin Stawiasz, Zeynep Toprak Deniz, Dieter F. Wendel, Matthew M. Ziegler
: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth. ISSCC (2014)
Robert A. Groves, Phillip J. Restle, Alan J. Drake, David Shan, Michael G. R. Thomson
microprocessor. CICC (2014)
Nancy Y. Zhou, Phillip J. Restle, Joseph N. Palumbo, Joseph N. Kozhaya, Haifeng Qian, Zhuo Li, Charles J. Alpert, Cliff C. N. Sze
Pacman: driving nonuniform clock grid loads for low-skew robust clock network. SLIP (2014)
Keith A. Jenkins, Phillip J. Restle, P. Z. Wang, D. Hogenmiller, David W. Boerstler, Thomas J. Bucelot
On-chip circuit for measuring multi-GHz clock signal waveforms. VTS (2013)
Liang-Teck Pang, Phillip J. Restle, Matthew R. Wordeman, Joel A. Silberman, Robert L. Franch, Gary W. Maier
A shorted global clock design for multi-GHz 3D stacked chips. VLSIC (2012)
Haifeng Qian, Phillip J. Restle, Joseph N. Kozhaya, Clifford L. Gunion
Subtractive Router for Tree-Driven-Grid Clocks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (6) (2012)
Joseph N. Kozhaya, Phillip J. Restle, Haifeng Qian
Myth busters: Microprocessor clocking is from Mars, ASICs clocking is from Venus. ICCAD (2011)
Dieter F. Wendel, Ronald N. Kalla, James D. Warnock, Robert Cargnoni, Sam G. Chu, Joachim G. Clabes, Daniel Dreps, David Hrusecky, Joshua Friedrich, Md. Saiful Islam, James A. Kahle, Jens Leenstra, Gaurav Mittal, Jose Paredes, Juergen Pille, Phillip J. Restle, Balaram Sinharoy, George Smith, William J. Starke, Scott A. Taylor, James Van Norstrand, Stephen Weitzel, Phillip G. Williams, Victor V. Zyuban
POWER7™, a Highly Parallel, Scalable Multi-Core High End Server Processor. IEEE J. Solid State Circuits 46 (1) (2011)
Cliff N. Sze, Phillip J. Restle, Gi-Joon Nam, Charles J. Alpert
Ispd2009 clock network synthesis contest. ISPD (2009)
Steven C. Chan, Phillip J. Restle, Thomas J. Bucelot, John S. Liberty, Stephen Weitzel, John M. Keaty, Brian K. Flachs, Richard Volant, Peter Kapusta, Jeffrey S. Zimmerman
A Resonant Global Clock Distribution for the Cell Broadband Engine Processor. IEEE J. Solid State Circuits 44 (1) (2009)
Robert L. Franch, Phillip J. Restle, James K. Norman, William V. Huott, Joshua Friedrich, R. Dixon, Steve Weitzel, K. van Goor, G. Salem
On-chip Timing Uncertainty Measurements on IBM Microprocessors. ITC (2008)
Steven C. Chan, Phillip J. Restle, Thomas J. Bucelot, Steve Weitzel, John M. Keaty, John S. Liberty, Brian K. Flachs, Richard Volant, Peter Kapusta, Jeffrey S. Zimmerman
A Resonant Global Clock Distribution for the Cell Broadband-Engine Processor. ISSCC (2008)
Rex Berridge, Robert M. Averill III, Arnold E. Barish, Michael A. Bowen, Peter J. Camporese, Jack DiLullo, Peter E. Dudley, Joachim Keinert, David W. Lewis, Robert D. Morel, Thomas E. Rosser, Nicole S. Schwartz, Philip Shephard, Howard H. Smith, Dave Thomas, Phillip J. Restle, John R. Ripley, Stephen L. Runyon, Patrick M. Williams
IBM POWER6 microprocessor physical design and design methodology. IBM J. Res. Dev. 51 (6) (2007)
Robert L. Franch, Phillip J. Restle, James K. Norman, William V. Huott, Joshua Friedrich, R. Dixon, Steve Weitzel, K. van Goor, G. Salem
On-chip timing uncertainty measurements on IBM microprocessors. ITC (2007)
Norman K. James, Phillip J. Restle, Joshua Friedrich, Bill Huott, Bradley D. McCredie
Comparison of Split-Versus Connected-Core Supplies in the POWER6 Microprocessor. ISSCC (2007)
Michael G. R. Thomson, Phillip J. Restle, Norman K. James
A 5GHz Duty-Cycle Correcting Clock Distribution Network for the POWER6 Microprocessor. ISSCC (2006)
Steven C. Chan, Kenneth L. Shepard, Phillip J. Restle
Distributed Differential Oscillators for Global Clock Networks. IEEE J. Solid State Circuits 41 (9) (2006)
Steven C. Chan, Kenneth L. Shepard, Phillip J. Restle
Uniform-phase uniform-amplitude resonant-load global clock distributions. IEEE J. Solid State Circuits 40 (1) (2005)
Gerald G. Lopez, Giovanni Fiorenza, Thomas J. Bucelot, Phillip J. Restle, Mary Yvonne Lanzerotti
Characterization of the impact of interconnect design on the capacitive load driven by a global clock distribution. ACM Great Lakes Symposium on VLSI (2005)
Phillip J. Restle, Kenneth L. Shepard
New Prospects for Clocking Synchronous and Quasi-Asynchronous Systems. ASYNC (2005)
Joachim G. Clabes, Joshua Friedrich, Mark Sweet, Jack DiLullo, Sam G. Chu, Donald W. Plass, James Dawson, Paul Muench, Larry Powell, Michael S. Floyd, Balaram Sinharoy, Mike Lee, Michael Goulet, James Wagoner, Nicole S. Schwartz, Stephen L. Runyon, Gary Gorman, Phillip J. Restle, Ronald N. Kalla, Joseph McGill, J. Steve Dodson
Design and implementation of the POWER5 microprocessor. DAC (2004)
Steven C. Chan, Kenneth L. Shepard, Phillip J. Restle
Design of Resonant Global Clock Distributions. ICCD (2003)
Xuejue Huang, Phillip J. Restle, Thomas J. Bucelot, Yu Cao, Tsu-Jae King, Chenming Hu
Loop-based interconnect modeling and optimization approach for multigigahertz clock network design. IEEE J. Solid State Circuits 38 (3) (2003)
James D. Warnock, John M. Keaty, John G. Petrovick, Joachim G. Clabes, Charles J. Kircher, Byron Krauter, Phillip J. Restle, Brian A. Zoric, Carl J. Anderson
The circuit and physical design of the POWER4 microprocessor. IBM J. Res. Dev. 46 (1) (2002)
Xuejue Huang, Phillip J. Restle, Thomas J. Bucelot, Yu Cao, Tsu-Jae King
Loop-based interconnect modeling and optimization approach for multi-GHz clock network design. CICC (2002)
Phillip J. Restle
Technical Visualizations in VLSI Design. DAC (2001)
Phillip J. Restle, Albert E. Ruehli, Steven G. Walker, George Papadopoulos
Full-wave PEEC time-domain method for the modeling of on-chipinterconnects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20 (7) (2001)
Phillip J. Restle, Albert E. Ruehli, Steven G. Walker
Multi-GHz interconnect effects in microprocessors. ISPD (2001)
Phillip J. Restle, Timothy G. McNamara, David A. Webber, Peter J. Camporese, Kwok F. Eng, Keith A. Jenkins, David H. Allen, Michael J. Rohn, Michael P. Quaranta, David W. Boerstler, Charles J. Alpert, Craig A. Carter, Roger N. Bailey, John G. Petrovick, Byron L. Krauter, Bradley D. McCredie
A clock distribution network for microprocessors. IEEE J. Solid State Circuits 36 (5) (2001)
Alina Deutsch, Paul W. Coteus, Gerard V. Kopcsay, Howard H. Smith, Christopher W. Surovic, Byron Krauter, Daniel C. Edelstein, Phillip J. Restle
On-chip wiring design challenges for gigahertz operation. Proc. IEEE 89 (4) (2001)
Phillip J. Restle, Albert E. Ruehli, Steven G. Walker
Dealing with Inductance in High-Speed Chip Design. DAC (1999)
Phillip J. Restle, Keith A. Jenkins, Alina Deutsch, Peter W. Cook
Measurement and modeling of on-chip transmission line effects in a 400 MHz microprocessor. IEEE J. Solid State Circuits 33 (4) (1998)
Phillip J. Restle, Joel R. Phillips, Ibrahim M. Elfadel
Interconnect in high speed designs: problems, methodologies and tools. ICCAD (1998)
Charles F. Webb, Carl J. Anderson, Leon J. Sigal, Kenneth L. Shepard, John S. Liptay, James D. Warnock, Brian W. Curran, Barry Krumm, Mark D. Mayo, Peter J. Camporese, Eric M. Schwarz, Mark S. Farrell, Phillip J. Restle, Robert M. Averill III, Timothy J. Slegel, William V. Huott, Yuen H. Chan, Bruce Wile, Thao N. Nguyen, Philip G. Emma, Daniel K. Beece, Ching-Te Chuang, Cyril Price
A 4.1-ns compact 54×54-b multiplier utilizing sign-select Booth encoders. IEEE J. Solid State Circuits 32 (11) (1997)