Charles J. Alpert

Publication Activity (10 Years)

Years Active: 1993-2018
Publications (10 Years): 9

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

ICCAD

ISPD

ASP-DAC

Publications

Yibo Lin, Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, Natarajan Viswanathan, Wen-Hao Liu, Zhuo Li, Charles J. Alpert, David Z. Pan
MrDP: Multiple-Row Detailed Placement of Heterogeneous-Sized Cells for Advanced Nodes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (6) (2018)
Charles J. Alpert, Wing-Kai Chow, Kwangsoo Han, Andrew B. Kahng, Zhuo Li, Derong Liu, Sriram Venkatesh
Prim-Dijkstra Revisited: Achieving Superior Timing-driven Routing Trees. ISPD (2018)
Yibo Lin, Bei Yu, Yi Zou, Zhuo Li, Charles J. Alpert, David Z. Pan
Stitch aware detailed placement for multiple E-beam lithography. Integr. 58 (2017)
Charles J. Alpert
Modern Challenges in Constructing Clocks. ISPD (2017)
Yibo Lin, Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, Natarajan Viswanathan, Wen-Hao Liu, Zhuo Li, Charles J. Alpert, David Z. Pan
MrDP: multiple-row detailed placement of heterogeneous-sized cells for advanced nodes. ICCAD (2016)
Yibo Lin, Bei Yu, Yi Zou, Zhuo Li, Charles J. Alpert, David Z. Pan
Stitch aware detailed placement for multiple e-beam lithography. ASP-DAC (2016)
Vijaykrishnan Narayanan, Charles J. Alpert, Sara Dailey
Editorial. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35 (3) (2016)
Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, Yibo Lin, Zhuo Li, Charles J. Alpert, David Z. Pan
Methodology for Standard Cell Compliance and Detailed Placement for Triple Patterning Lithography. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (5) (2015)
Vijaykrishnan Narayanan, Charles J. Alpert, Sara Dailey
Editorial. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (1) (2015)
Yaoguang Wei, Cliff C. N. Sze, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Lakshmi N. Reddy, Andrew D. Huber, Gustavo E. Téllez, Douglas Keller, Sachin S. Sapatnekar
Techniques for scalable and effective routability evaluation. ACM Trans. Design Autom. Electr. Syst. 19 (2) (2014)
Nancy Y. Zhou, Phillip J. Restle, Joseph N. Palumbo, Joseph N. Kozhaya, Haifeng Qian, Zhuo Li, Charles J. Alpert, Cliff C. N. Sze
Pacman: driving nonuniform clock grid loads for low-skew robust clock network. SLIP (2014)
Xing Wei, Wai-Chung Tang, Yu-Liang Wu, Cliff C. N. Sze, Charles J. Alpert
Mountain-mover: An intuitive logic shifting heuristic for improving timing slack violating paths. ASP-DAC (2013)
Samuel I. Ward, Natarajan Viswanathan, Nancy Y. Zhou, Cliff C. N. Sze, Zhuo Li, Charles J. Alpert, David Z. Pan
Clock power minimization using structured latch templates and decision tree induction. ICCAD (2013)
Wen-Hao Liu, Yaoguang Wei, Cliff C. N. Sze, Charles J. Alpert, Zhuo Li, Yih-Lang Li, Natarajan Viswanathan
Routing congestion estimation with real design constraints. DAC (2013)
Myung-Chul Kim, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert
ICCAD-2013 CAD contest in placement finishing and benchmark suite. ICCAD (2013)
Yaoguang Wei, Zhuo Li, Cliff C. N. Sze, Shiyan Hu, Charles J. Alpert, Sachin S. Sapatnekar
CATALYST: planning layer directives for effective design closure. DATE (2013)
Samuel I. Ward, Myung-Chul Kim, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Earl E. Swartzlander Jr., David Z. Pan
Structure-Aware Placement Techniques for Designs With Datapaths. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (2) (2013)
Myung-Chul Kim, Natarajan Viswanathan, Charles J. Alpert, Igor L. Markov, Shyam Ramji
MAPLE: multilevel adaptive placement for mixed-size designs. ISPD (2012)
Natarajan Viswanathan, Charles J. Alpert, Cliff C. N. Sze, Zhuo Li, Yaoguang Wei
The DAC 2012 routability-driven placement contest and benchmark suite. DAC (2012)
Yaoguang Wei, Cliff C. N. Sze, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Lakshmi N. Reddy, Andrew D. Huber, Gustavo E. Téllez, Douglas Keller, Sachin S. Sapatnekar
GLARE: global and local wiring aware routability evaluation. DAC (2012)
Xing Wei, Wai-Chung Tang, Yu-Liang Wu, Cliff C. N. Sze, Charles J. Alpert
WRIP: logic restructuring techniques for wirelength-driven incremental placement. ACM Great Lakes Symposium on VLSI (2012)
Samuel I. Ward, Myung-Chul Kim, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Earl E. Swartzlander Jr., David Z. Pan
Keep it straight: teaching placement how to better handle designs with datapaths. ISPD (2012)
Zhuo Li, Charles J. Alpert, Gi-Joon Nam, Cliff C. N. Sze, Natarajan Viswanathan, Nancy Y. Zhou
Guiding a physical design closure system to produce easier-to-route designs with more predictable timing. DAC (2012)
Natarajan Viswanathan, Charles J. Alpert, Cliff C. N. Sze, Zhuo Li, Yaoguang Wei
ICCAD-2012 CAD contest in design hierarchy aware routability-driven placement and benchmark suite. ICCAD (2012)
Charles J. Alpert, Zhuo Li, Gi-Joon Nam, Chin Ngai Sze, Natarajan Viswanathan, Samuel I. Ward
Placement: Hot or Not? ICCAD (2012)
David A. Papa, Charles J. Alpert, Cliff C. N. Sze, Zhuo Li, Natarajan Viswanathan, Gi-Joon Nam, Igor L. Markov
Physical Synthesis with Clock-Network Optimization for Large Systems on Chips. IEEE Micro 31 (4) (2011)
Samuel I. Ward, David A. Papa, Zhuo Li, Cliff N. Sze, Charles J. Alpert, Earl E. Swartzlander Jr.
Quantifying academic placer performance on custom designs. ISPD (2011)
Nancy Ying Zhou, Charles J. Alpert, Zhuo Li, Cliff N. Sze, Louise Trevillyan
Shedding Physical Synthesis Area Bloat. VLSI Design 2011 (2011)
Natarajan Viswanathan, Charles J. Alpert, Cliff C. N. Sze, Zhuo Li, Gi-Joon Nam, Jarrod A. Roy
The ISPD-2011 routability-driven placement contest and benchmark suite. ISPD (2011)
Yi-Lin Chuang, Gi-Joon Nam, Charles J. Alpert, Yao-Wen Chang, Jarrod A. Roy, Natarajan Viswanathan
Design-hierarchy aware mixed-size placement for routability optimization. ICCAD (2010)
Tanuj Jindal, Charles J. Alpert, Jiang Hu, Zhuo Li, Gi-Joon Nam, Charles B. Winn
Detecting tangled logic structures in VLSI netlists. DAC (2010)
Natarajan Viswanathan, Gi-Joon Nam, Jarrod A. Roy, Zhuo Li, Charles J. Alpert, Shyam Ramji, Chris Chu
ITOP: integrating timing optimization within placement. ISPD (2010)
Charles J. Alpert, Zhuo Li, Michael D. Moffitt, Gi-Joon Nam, Jarrod A. Roy, Gustavo E. Téllez
What makes a design difficult to route. ISPD (2010)
David A. Papa, Michael D. Moffitt, Charles J. Alpert, Igor L. Markov
Speeding Up Physical Synthesis with Transactional Timing Analysis. IEEE Des. Test Comput. 27 (5) (2010)
Zhuo Li, David A. Papa, Charles J. Alpert, Shiyan Hu, Weiping Shi, Cliff C. N. Sze, Nancy Ying Zhou
Ultra-fast interconnect driven cell cloning for minimizing critical path delay. ISPD (2010)
Taraneh Taghavi, Zhuo Li, Charles J. Alpert, Gi-Joon Nam, Andrew D. Huber, Shyam Ramji
New placement prediction and mitigation techniques for local routing congestion. ICCAD (2010)
Shiyan Hu, Zhuo Li, Charles J. Alpert
A fully polynomial time approximation scheme for timing driven minimum cost buffer insertion. DAC (2009)
Jarrod A. Roy, Natarajan Viswanathan, Gi-Joon Nam, Charles J. Alpert, Igor L. Markov
CRISP: Congestion reduction by iterated spreading during placement. ICCAD (2009)
Cliff N. Sze, Phillip J. Restle, Gi-Joon Nam, Charles J. Alpert
Ispd2009 clock network synthesis contest. ISPD (2009)
Shiyan Hu, Zhuo Li, Charles J. Alpert
A Fully Polynomial-Time Approximation Scheme for Timing-Constrained Minimum Cost Layer Assignment. IEEE Trans. Circuits Syst. II Express Briefs (7) (2009)
Shiyan Hu, Zhuo Li, Charles J. Alpert
A faster approximation scheme for timing driven minimum cost layer assignment. ISPD (2009)
Tao Luo, David A. Papa, Zhuo Li, Chin Ngai Sze, Charles J. Alpert, David Z. Pan
Pyramids: an efficient computational geometry-based approach for timing-driven placement. ICCAD (2008)
David A. Papa, Tao Luo, Michael D. Moffitt, Chin Ngai Sze, Zhuo Li, Gi-Joon Nam, Charles J. Alpert, Igor L. Markov
RUMBLE: an incremental, timing-driven, physical-synthesis optimization algorithm. ISPD (2008)
David A. Papa, Tao Luo, Michael D. Moffitt, Chin Ngai Sze, Zhuo Li, Gi-Joon Nam, Charles J. Alpert, Igor L. Markov
RUMBLE: An Incremental Timing-Driven Physical-Synthesis Optimization Algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (12) (2008)
Shiyan Hu, Zhuo Li, Charles J. Alpert
A polynomial time approximation scheme for timing constrained minimum cost layer assignment. ICCAD (2008)
Zhuo Li, Charles J. Alpert, Shiyan Hu, Tuhin Muhmud, Stephen T. Quay, Paul G. Villarrubia
Fast interconnect synthesis with layer assignment. ISPD (2008)
Michael D. Moffitt, David A. Papa, Zhuo Li, Charles J. Alpert
Path smoothing via discrete optimization. DAC (2008)
Natarajan Viswanathan, Gi-Joon Nam, Charles J. Alpert, Paul Villarrubia, Haoxing Ren, Chris C. N. Chu
RQL: Global Placement via Relaxed Quadratic Spreading and Linearization. DAC (2007)
Haoxing Ren, David Z. Pan, Charles J. Alpert, Gi-Joon Nam, Paul G. Villarrubia
Hippocrates: First-Do-No-Harm Detailed Placement. ASP-DAC (2007)
Shrirang K. Karandikar, Charles J. Alpert, Mehmet Can Yildiz, Paul Villarrubia, Stephen T. Quay, T. Mahmud
Fast Electrical Correction Using Resizing and Buffering. ASP-DAC (2007)
Charles J. Alpert, Shrirang K. Karandikar, Zhuo Li, Gi-Joon Nam, Stephen T. Quay, Haoxing Ren, Cliff C. N. Sze, Paul G. Villarrubia, Mehmet Can Yildiz
Techniques for Fast Physical Synthesis. Proc. IEEE 95 (3) (2007)
Charles J. Alpert, Chris C. N. Chu, Paul G. Villarrubia
The coming of age of physical synthesis. ICCAD (2007)
Charles J. Alpert, Shrirang K. Karandikar, Zhuo Li, Gi-Joon Nam, Stephen T. Quay, Haoxing Ren, Cliff C. N. Sze, Paul G. Villarrubia, Mehmet Can Yildiz
The nuts and bolts of physical synthesis. SLIP (2007)
Haoxing Ren, David Z. Pan, Charles J. Alpert, Paul G. Villarrubia, Gi-Joon Nam
Diffusion-Based Placement Migration With Application on Legalization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (12) (2007)
Chin Ngai Sze, Charles J. Alpert, Jiang Hu, Weiping Shi
Path-Based Buffer Insertion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (7) (2007)
Zhuo Li, Charles J. Alpert, Stephen T. Quay, Sachin S. Sapatnekar, Weiping Shi
Probabilistic Congestion Prediction with Partial Blockages. ISQED (2007)
Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li, Weiping Shi, Chin Ngai Sze
Fast Algorithms for Slew-Constrained Minimum Cost Buffering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (11) (2007)
Gi-Joon Nam, Sherief Reda, Charles J. Alpert, Paul Villarrubia, Andrew B. Kahng
A Fast Hierarchical Quadratic Placement Algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (4) (2006)
Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Cliff C. N. Sze
Accurate estimation of global buffer delay within a floorplan. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (6) (2006)
Charles J. Alpert, Andrew B. Kahng, Cliff C. N. Sze, Qinke Wang
Timing-driven Steiner trees are (practically) free. DAC (2006)
Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li, Weiping Shi, Cliff C. N. Sze
Fast algorithms for slew constrained minimum cost buffering. DAC (2006)
Cliff C. N. Sze, Charles J. Alpert, Jiang Hu, Weiping Shi
Path based buffer insertion. DAC (2005)
Charles J. Alpert, Gi-Joon Nam, Paul Villarribua, Mehmet Can Yildiz
Placement stability metrics. ASP-DAC (2005)
Haoxing Ren, David Zhigang Pan, Charles J. Alpert, Paul Villarrubia
Diffusion-based placement migration. DAC (2005)
Rajeev R. Rao, David T. Blaauw, Dennis Sylvester, Charles J. Alpert, Sani R. Nassif
An efficient surface-based low-power buffer insertion algorithm. ISPD (2005)
Charles J. Alpert, Andrew B. Kahng, Gi-Joon Nam, Sherief Reda, Paul Villarrubia
A semi-persistent clustering technique for VLSI circuit placement. ISPD (2005)
Ganesh Venkataraman, Nikhil Jayakumar, Jiang Hu, Peng Li, Sunil P. Khatri, Anand Rajaram, Patrick McGuinness, Charles J. Alpert
Practical techniques to reduce skew and its variations in buffered clock networks. ICCAD (2005)
Zhuo Li, Cliff C. N. Sze, Charles J. Alpert, Jiang Hu, Weiping Shi
Making fast buffer insertion even faster via approximation techniques. ASP-DAC (2005)
Tao Luo, Haoxing Ren, Charles J. Alpert, David Zhigang Pan
Computational geometry based placement migration. ICCAD (2005)
Gi-Joon Nam, Charles J. Alpert, Paul Villarrubia, Bruce Winter, Mehmet Can Yildiz
The ISPD2005 placement contest and benchmark suite. ISPD (2005)
Charles J. Alpert, Frank Liu, Chandramouli V. Kashyap, Anirudh Devgan
Closed-form delay and slew metrics made easy. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (12) (2004)
Charles J. Alpert, Chris C. N. Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen T. Quay
Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (1) (2004)
Cliff C. N. Sze, Jiang Hu, Charles J. Alpert
A place and route aware buffered Steiner tree construction. ASP-DAC (2004)
Charles J. Alpert, Milos Hrkic, Stephen T. Quay
A fast algorithm for identifying good buffer insertion candidate locations. ISPD (2004)
Frank Liu, Chandramouli V. Kashyap, Charles J. Alpert
A delay metric for RC circuits based on the Weibull distribution. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (3) (2004)
Weiping Shi, Zhuo Li, Charles J. Alpert
Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost. ASP-DAC (2004)
Chandramouli V. Kashyap, Charles J. Alpert, Frank Liu, Anirudh Devgan
Closed-form expressions for extending step delay and slew metrics to ramp inputs for RC trees. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (4) (2004)
Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Cliff C. N. Sze
Accurate estimation of global buffer delay within a floorplan. ICCAD (2004)
Charles J. Alpert, Milos Hrkic, Jiang Hu, Stephen T. Quay
Fast and flexible buffer trees that navigate the physical layout environment. DAC (2004)
Charles J. Alpert, Gopal Gandham, Milos Hrkic, Jiang Hu, Stephen T. Quay, Cliff C. N. Sze
Porosity-aware buffered Steiner tree construction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (4) (2004)
Charles J. Alpert, Gi-Joon Nam, Paul G. Villarrubia
Effective free space management for cut-based placement via analytical constraint generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22 (10) (2003)
Jiang Hu, Charles J. Alpert, Stephen T. Quay, Gopal Gandham
Buffer insertion with adaptive blockage avoidance. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22 (4) (2003)
Soha Hassoun, Charles J. Alpert
Optimal path routing in single- and multiple-clock domain systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22 (11) (2003)
Charles J. Alpert, Gopal Gandham, Milos Hrkic, Jiang Hu, Stephen T. Quay
Porosity aware buffered steiner tree construction. ISPD (2003)
Charles J. Alpert, Frank Liu, Chandramouli V. Kashyap, Anirudh Devgan
Delay and slew metrics using the lognormal distribution. DAC (2003)
Charles J. Alpert, Sachin S. Sapatnekar
Guest editorial. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22 (4) (2003)
Chandramouli V. Kashyap, Charles J. Alpert, Frank Liu, Anirudh Devgan
Closed form expressions for extending step delay and slew metrics to ramp inputs. ISPD (2003)
Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Paul Villarrubia
A practical methodology for early buffer and wire resource allocation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22 (5) (2003)
Charles J. Alpert, Andrew B. Kahng, Bao Liu, Ion I. Mandoiu, Alexander Zelikovsky
Minimum buffered routing with bounded capacitive load for slew rate and reliability control. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22 (3) (2003)
Charles J. Alpert, Chris C. N. Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen T. Quay
Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. ISPD (2002)
Charles J. Alpert, Anirudh Devgan, John P. Fishburn, Stephen T. Quay
Correction to "interconnect synthesis without wire tapering". IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21 (4) (2002)
Charles J. Alpert, Gi-Joon Nam, Paul Villarrubia
Free space management for cut-based placement. ICCAD (2002)
Suresh Raman, Sachin S. Sapatnekar, Charles J. Alpert
Probability-driven routing in a datapath environment. Integr. 31 (2) (2002)
Frank Liu, Chandramouli V. Kashyap, Charles J. Alpert
A delay metric for RC circuits based on the Weibull distribution. ICCAD (2002)
Soha Hassoun, Charles J. Alpert, Meera Thiagarajan
Optimal buffered routing path constructions for single and multiple clock domain systems. ICCAD (2002)
Jiang Hu, Charles J. Alpert, Stephen T. Quay, Gopal Gandham
Buffer insertion with adaptive blockage avoidance. ISPD (2002)
Chandramouli V. Kashyap, Charles J. Alpert, Frank Liu, Anirudh Devgan
PERI: a technique for extending delay and slew metrics to ramp inputs. Timing Issues in the Specification and Synthesis of Digital Systems (2002)
Charles J. Alpert, Milos Hrkic, Jiang Hu, Andrew B. Kahng, John Lillis, Bao Liu, Stephen T. Quay, Sachin S. Sapatnekar, A. J. Sullivan, Paul Villarrubia
Buffered Steiner trees for difficult instances. ISPD (2001)
Charles J. Alpert, Gopal Gandham, Jiang Hu, José Luis Neves, Stephen T. Quay, Sachin S. Sapatnekar
Steiner tree optimization for buffers, blockages, and bays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20 (4) (2001)
Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Paul Villarrubia
A Practical Methodology for Early Buffer and Wire Resource Allocation. DAC (2001)

Charles J. Alpert.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Top Topics

Top Venues

Charles J. Alpert