Gustavo E. Téllez

Publication Activity (10 Years)

Years Active: 1994-2022
Publications (10 Years): 5

Top Topics

Alternating Optimization

Routing Algorithm

Top Venues

ACM Trans. Design Autom. Electr. Syst.

Publications

Diwesh Pandey, Gustavo E. Téllez, James Leland
LEO: Line End Optimizer for Sub-7nm Technology Nodes. ISPD (2022)
Chau-Chin Huang, Gustavo E. Téllez, Gi-Joon Nam, Yao-Wen Chang
Latch Clustering for Timing-Power Co-Optimization. DAC (2020)
Hua Xiang, Gi-Joon Nam, Gustavo E. Téllez, Shyam Ramji, Xiaoqing Xu
Self-Aligned Double-Patterning Aware Legalization. DATE (2020)
Alexey Lvov, Gustavo E. Téllez, Gi-Joon Nam
On Coloring and Colorability Analysis of Integrated Circuits with Triple and Quadruple Patterning Techniques. ISPD (2018)
Jiang Hu, Ying Zhou, Yaoguang Wei, Stephen T. Quay, Lakshmi N. Reddy, Gustavo E. Téllez, Gi-Joon Nam
Interconnect Optimization Considering Multiple Critical Paths. ISPD (2018)
Markus Ahrens, Michael Gester, Niko Klewinghaus, Dirk Müller, Sven Peyer, Christian Schulte, Gustavo E. Téllez
Detailed Routing Algorithms for Advanced Technology Nodes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (4) (2015)
Yaoguang Wei, Cliff C. N. Sze, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Lakshmi N. Reddy, Andrew D. Huber, Gustavo E. Téllez, Douglas Keller, Sachin S. Sapatnekar
Techniques for scalable and effective routability evaluation. ACM Trans. Design Autom. Electr. Syst. 19 (2) (2014)
Yaoguang Wei, Cliff C. N. Sze, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Lakshmi N. Reddy, Andrew D. Huber, Gustavo E. Téllez, Douglas Keller, Sachin S. Sapatnekar
GLARE: global and local wiring aware routability evaluation. DAC (2012)
Joshua Friedrich, Ruchir Puri, Uwe Brandt, Markus Bühler, Jack DiLullo, Jeremy Hopkins, Mozammel Hossain, Michael A. Kazda, Joachim Keinert, Zahi M. Kurzum, Douglass Lamb, Alice Lee, Frank Musante, Jens Noack, Peter J. Osler, Stephen D. Posluszny, Haifeng Qian, Shyam Ramji, Vasant B. Rao, Lakshmi N. Reddy, Haoxing Ren, Thomas E. Rosser, Benjamin R. Russell, Cliff C. N. Sze, Gustavo E. Téllez
Design methodology for the IBM POWER7 microprocessor. IBM J. Res. Dev. 55 (3) (2011)
Charles J. Alpert, Zhuo Li, Michael D. Moffitt, Gi-Joon Nam, Jarrod A. Roy, Gustavo E. Téllez
What makes a design difficult to route. ISPD (2010)
Amir H. Farrahi, Chunhong Chen, Ankur Srivastava, Gustavo E. Téllez, Majid Sarrafzadeh
Activity-driven clock design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20 (6) (2001)
John A. Darringer, Evan E. Davidson, David J. Hathaway, Bernd Koenemann, Mark A. Lavin, Joseph K. Morrell, Khalid Rahmat, Wolfgang Roesner, Erich C. Schanzenbach, Gustavo E. Téllez, Louise Trevillyan
EDA in IBM: past, present, and future. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19 (12) (2000)
Amir H. Farrahi, Gustavo E. Téllez, Majid Sarrafzadeh
Exploiting Sleep Mode for Memory Partitioning and Other Applications. VLSI Design 1998 (3) (1998)
Gustavo E. Téllez, Majid Sarrafzadeh
On Rectilinear Distance-Preserving Trees. VLSI Design 1998 (1) (1998)
Gustavo E. Téllez, Majid Sarrafzadeh
Minimal buffer insertion in clock trees with skew and slew rate constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16 (4) (1997)
Majid Sarrafzadeh, David A. Knol, Gustavo E. Téllez
A delay budgeting algorithm ensuring maximum flexibility in placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16 (11) (1997)
Majid Sarrafzadeh, David A. Knol, Gustavo E. Téllez
Unification of Budgeting and Placement. DAC (1997)
Fook-Luen Heng, Zhan Chen, Gustavo E. Téllez
A VLSI artwork legalization technique based on a new criterion of minimum layout perturbation. ISPD (1997)
Gustavo E. Téllez, Amir H. Farrahi, Majid Sarrafzadeh
Activity-driven clock design for low power circuits. ICCAD (1995)
Gustavo E. Téllez, Majid Sarrafzadeh
On Rectilinear Distance-Preserving Trees. ISCAS (1995)
Amir H. Farrahi, Gustavo E. Téllez, Majid Sarrafzadeh
Memory Segmentation to Exploit Sleep Mode Operation. DAC (1995)
Gustavo E. Téllez, Majid Sarrafzadeh
Clock period constrained minimal buffer insertion in clock trees. ICCAD (1994)