Chunhong Chen

Publication Activity (10 Years)

Years Active: 1999-2022
Publications (10 Years): 11

Top Topics

False Alarm Probability

Reliability Analysis

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Suoyue Zhan, Chunhong Chen
A hybrid method for signal probability and reliability estimation with combinational circuits. Integr. 87 (2022)
Suoyue Zhan, Chunhong Chen
An Efficient Method for Sequential Circuit Reliability Estimation. MWSCAS (2022)
Chen Zhang, Huapeng Wu, Chunhong Chen
Area-Efficient Finite Field Multiplication Using Hybrid SET-MOS Technology. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (11) (2022)
Chunhong Chen, Suoyue Zhan
A Hybrid Method for Signal Probability Estimation with Combinational Circuits. APCCAS (2022)
Suoyue Zhan, Chunhong Chen
Circuit Reliability Analysis with Considerations of Aging Effect. SBCCI (2022)
Chen Zhang, Chunhong Chen, Huapeng Wu
Area-Efficient Finite Field Multiplication in $\text{GF} (2^{n})$ Using Single-Electron Transistors. APCCAS (2021)
Khawja Sikander, Suoyue Zhan, Chunhong Chen
An Analytical Model for Circuit Reliability Estimation. MWSCAS (2021)
Suoyue Zhan, Khawja Sikander, Chunhong Chen
Allocating Gate Reliability for Circuit Reliability Optimization. MWSCAS (2019)
Lin Li, Chunhong Chen
Modeling and Application for Negative-Differential-Conductance Devices with Single-Electron Technology. MWSCAS (2018)
Chunhong Chen, Jinchen Cai, Suoyue Zhan
A Triple-Point Model for Circuit-Level Reliability Analysis. ISCAS (2018)
Jinchen Cai, Chunhong Chen
Circuit Reliability Analysis Using Signal Reliability Correlations. QRS Companion (2017)
Ran Xiao, Chunhong Chen
Power optimization design for probabilistic logic circuits. ISCAS (2015)
Chunhong Chen, Ran Xiao
A fast model for analysis and improvement of gate-level circuit reliability. Integr. 50 (2015)
Ran Xiao, Chunhong Chen
Implementation of the conscience mechanism using single-electron transfer in competitive learning. ISCAS (2014)
Ran Xiao, Chunhong Chen
Gate-Level Circuit Reliability Analysis: A Survey. VLSI Design 2014 (2014)
Guoqing Deng, Chunhong Chen
A SET/MOS Hybrid Multiplier Using Frequency Synthesis. IEEE Trans. Very Large Scale Integr. Syst. 21 (9) (2013)
Guoqing Deng, Chunhong Chen
Binary Multiplication Using Hybrid MOS and Multi-Gate Single-Electron Transistors. IEEE Trans. Very Large Scale Integr. Syst. 21 (9) (2013)
Chia-Chin Liu, Chunhong Chen
An ultra-low power voltage regulator for RFID application. MWSCAS (2013)
Shu-Yi Wong, Chunhong Chen
Power efficient multi-stage CMOS rectifier design for UHF RFID tags. Integr. 44 (3) (2011)
Shu-Yi Wong, Chunhong Chen, Q. M. Jonathan Wu
Low Power Chien Search for BCH Decoder Using RT-Level Power Management. IEEE Trans. Very Large Scale Integr. Syst. 19 (2) (2011)
Chunni Dai, Meng Yao, Zhujie Xie, Chunhong Chen, Jingao Liu
Parameter optimization for growth model of greenhouse crop using genetic algorithms. Appl. Soft Comput. 9 (1) (2009)
Shu-Yi Wong, Chunhong Chen, Q. M. Jonathan Wu
Power-management-based Chien search for low power BCH decoder. ISLPED (2009)
Venketeshwaran Puthucode, Chunhong Chen
An experimental study on multi-island structures for single-electron tunneling based threshold logic. ISCAS (2008)
Mohammed Berhea, Chunhong Chen, Q. M. Jonathan Wu
Protocol-level performance analysis for anti-collision protocols in RFID systems. ISCAS (2008)
Shun Li, Feng Zhou, Chunhong Chen, Hua Chen, Yipin Wu
Quasi-Static Energy Recovery Logic with Single Power-Clock Supply. ISCAS (2007)
Yanjie Mao, Chunhong Chen
Performance Evaluation and Optimization of Full Adders with Single-Electron Technology. CCECE (2006)
Chunhong Chen, Zheng Li
A low-power CMOS analog multiplier. IEEE Trans. Circuits Syst. II Express Briefs (2) (2006)
Jialin Mi, Chunhong Chen, H. K. Kwan
Power-oriented delay budgeting for combinational circuits. ISCAS (2006)
Jialin Mi, Chunhong Chen
Finite State Machine Implementation with Single-Electron Tunneling Technology. ISVLSI (2006)
Jialin Mi, Chunhong Chen
Power-Oriented Delay Budgeting for Combinational Circuits. ISVLSI (2006)
Chunhong Chen, Jiang Zhao, Majid Ahmadi
A Novel State Encoding Algorithm for Low Power Implementation. J. Circuits Syst. Comput. 14 (3) (2005)
Feng Zhou, Chunhong Chen, Dawei Jin, Chenling Huang, Hao Min
Evaluating and optimizing power consumption of anti-collision protocols for applications in RFID systems. ISLPED (2004)
Ankur Srivastava, Ryan Kastner, Chunhong Chen, Majid Sarrafzadeh
Timing driven gate duplication. IEEE Trans. Very Large Scale Integr. Syst. 12 (1) (2004)
Chunhong Chen, Jiang Zhao, Majid Ahmadi
A semi-Gray encoding algorithm for low-power state assignment. ISCAS (5) (2003)
Chunhong Chen, Jiang Zhao, Majid Ahmadi
Probability-based approach to rectilinear Steiner tree problems. IEEE Trans. Very Large Scale Integr. Syst. 10 (6) (2002)
Chunhong Chen, Majid Sarrafzadeh
Power-Manageable Scheduling Technique for Control Dominated High-Level Synthesis. DATE (2002)
Chunhong Chen, Xiaojian Yang, Majid Sarrafzadeh
Predicting potential performance for digital circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21 (3) (2002)
Chunhong Chen, Elaheh Bozorgzadeh, Ankur Srivastava, Majid Sarrafzadeh
Budget Management with Applications. Algorithmica 34 (3) (2002)
Chunhong Chen
Physical design with multiple on-chip voltages. ISPD (2002)
Chunhong Chen
Probabilistic Analysis of Rectilinear Steiner Trees. VLSI Design (2002)
Chunhong Chen, Changjun Kang, Majid Sarrafzadeh
Activity-sensitive clock tree construction for low power. ISLPED (2002)
Ankur Srivastava, Chunhong Chen, Majid Sarrafzadeh
Timing driven gate duplication in technology independent phase. ASP-DAC (2001)
Amir H. Farrahi, Chunhong Chen, Ankur Srivastava, Gustavo E. Téllez, Majid Sarrafzadeh
Activity-driven clock design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20 (6) (2001)
Chunhong Chen, Ankur Srivastava, Majid Sarrafzadeh
On gate level power optimization using dual-supply voltages. IEEE Trans. Very Large Scale Integr. Syst. 9 (5) (2001)
Anshuman Nayak, Malay Haldar, Prith Banerjee, Chunhong Chen, Majid Sarrafzadeh
Power Optimization of Delay Constrained Circuits. VLSI Design 2001 (2) (2001)
Chunhong Chen, Majid Sarrafzadeh
Power reduction by simultaneous voltage scaling and gate sizing. ASP-DAC (2000)
Chunhong Chen, Xiaojian Yang, Majid Sarrafzadeh
Potential Slack: An Effective Metric of Combinational Circuit Performance. ICCAD (2000)
Chunhong Chen, Majid Sarrafzadeh
An Effective Algorithm for Gate-Level Power-Delay Tradeoff Using Two Voltages. ICCD (1999)
Chunhong Chen, Majid Sarrafzadeh
Provably good algorithm for low power consumption with dual supply voltages. ICCAD (1999)