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Power reduction by simultaneous voltage scaling and gate sizing.

Chunhong ChenMajid Sarrafzadeh
Published in: ASP-DAC (2000)
Keyphrases
  • power reduction
  • power losses
  • power consumption
  • low power
  • cmos technology
  • low voltage
  • power dissipation
  • power saving
  • field effect transistors
  • silicon dioxide
  • high speed
  • low cost