Wolfgang Roesner

Publication Activity (10 Years)

Years Active: 1985-2024
Publications (10 Years): 3

Top Topics

Industry Standard

Verification Method

Floating Point Unit

Dynamic Random Access Memory

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Arun Joseph, Pretty Mariam Jacob, Matthias Klein, Wolfgang Roesner
Efficient Aspect Verification and Debugging of High-Performance Microprocessor Designs. IEEE Des. Test 41 (3) (2024)
Maya H. Safieddine, Fadi A. Zaraket, Rouwaida Kanj, Ali S. Elzein, Wolfgang Roesner
Verification at RTL Using Separation of Design Concerns. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38 (8) (2019)
Stephen Bergman, Gabor Bobok, Walter Kowalski, Shlomit Koyfman, Shiri Moran, Ziv Nevo, Avigail Orni, Viresh Paruthi, Wolfgang Roesner, Gil Shurek, Vasantha Vuyyuru
Designer-level verification: an industrial experience story. DATE (2015)
Amir Nahir, Manoj Dusanapudi, Shakti Kapoor, Kevin Reick, Wolfgang Roesner, Klaus-Dieter Schubert, Keith Sharp, Greg Wetli
Post-Silicon Validation of the IBM POWER8 Processor. DAC (2014)
Christopher A. Krygowski, Dean G. Bair, Rebecca M. Gott, M. H. Decker, A. V. Giri, Christian Habermann, Matthias Heizmann, Stefan Letz, William J. Lewis, Steven M. Licker, H. Mallar, Edward C. McCain, Wolfgang Roesner, N. Siddique, A. E. Seigler, Brian W. Thompto, K. Weber, Ralf Winkelmann
Functional verification of the IBM System z10 processor chipset. IBM J. Res. Dev. 53 (1) (2009)
Hiroyuki Yagi, Wolfgang Roesner, Tim Kogel, Eshel Haritan, Hidekazu Tangi, Michael McNamara, Gary Smith, Nikil D. Dutt, Giovanni Mancini
ESL hand-off: fact or EDA fiction? DAC (2008)
Hans-Werner Anderson, Hans Kriese, Wolfgang Roesner, Klaus-Dieter Schubert
Configurable system simulation model build comprising packaging design data. IBM J. Res. Dev. 48 (3-4) (2004)
Wolfgang Roesner
What Is beyond the RTL Horizon for Microprocessor and System Design? CHARME (2003)
John M. Ludden, Wolfgang Roesner, Gerry M. Heiling, John R. Reysa, Jonathan R. Jackson, Bing-Lun Chu, Michael L. Behm, Jason Baumgartner, Richard D. Peterson, Jamee Abdulhafiz, William E. Bucy, John H. Klaus, Danny J. Klema, Tien N. Le, F. Danette Lewis, Philip E. Milling, Lawrence A. McConville, Bradley S. Nelson, Viresh Paruthi, Travis W. Pouarz, Audre D. Romonosky, Jeff Stuecheli, Kent D. Thompson, Dave W. Victor, Bruce Wile
Functional verification of the POWER4 microprocessor and POWER4 multiprocessor system. IBM J. Res. Dev. 46 (1) (2002)
John A. Darringer, Evan E. Davidson, David J. Hathaway, Bernd Koenemann, Mark A. Lavin, Joseph K. Morrell, Khalid Rahmat, Wolfgang Roesner, Erich C. Schanzenbach, Gustavo E. Téllez, Louise Trevillyan
EDA in IBM: past, present, and future. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19 (12) (2000)
Wolfgang Roesner
The logic design language and verification environment for the VLSI-/370. Microprocess. Microprogramming 24 (1-5) (1988)
Wolfgang Roesner
SESPATH: An ER Manipulation Language. ER (1985)