Viresh Paruthi

Publication Activity (10 Years)

Years Active: 1998-2015
Publications (10 Years): 0

Top Topics

Formal Verification

Algebraic Geometry

Top Venues

IBM J. Res. Dev.

Formal Methods Syst. Des.

Publications

Klaus-Dieter Schubert, John M. Ludden, S. Ayub, J. Behrend, B. Brock, Fady Copty, S. M. German, Oz Hershkovitz, H. Horbach, Jonathan R. Jackson, K. Keuerleber, J. Koesters, L. S. Leitner, G. B. Meil, Charles Meissner, Ronny Morad, Amir Nahir, Viresh Paruthi, Richard D. Peterson, Randall R. Pratt, Michal Rimon, John Schumann
Solutions to IBM POWER8 verification challenges. IBM J. Res. Dev. 59 (1) (2015)
Stephen Bergman, Gabor Bobok, Walter Kowalski, Shlomit Koyfman, Shiri Moran, Ziv Nevo, Avigail Orni, Viresh Paruthi, Wolfgang Roesner, Gil Shurek, Vasantha Vuyyuru
Designer-level verification: an industrial experience story. DATE (2015)
Alexey Lvov, Luis Alfonso Lastras-Montaño, Barry M. Trager, Viresh Paruthi, Robert Shadowen, Ali El-Zein
Verification of Galois field based circuits by formal reasoning based on computational algebraic geometry. Formal Methods Syst. Des. 45 (2) (2014)
Udo Krautz, Viresh Paruthi, Anand Arunagiri, Sujeet Kumar, Shweta Pujar, Tina Babinsky
Automatic Verification of Floating Point Units. DAC (2014)
Alexey Lvov, Luis Alfonso Lastras-Montaño, Viresh Paruthi, Robert Shadowen, Ali El-Zein
Formal verification of error correcting circuits using computational algebraic geometry. FMCAD (2012)
Jun Sawada, Peter Sandon, Viresh Paruthi, Jason Baumgartner, Michael L. Case, Hari Mony
Hybrid verification of a hardware modular reduction engine. FMCAD (2011)
Gadiel Auerbach, Fady Copty, Viresh Paruthi
Formal verification of arbiters using property strengthening and underapproximations. FMCAD (2010)
Viresh Paruthi
Large-scale application of formal verification: From fiction to fact. FMCAD (2010)
Krishnan Kailas, Viresh Paruthi, Brian Monwai
Formal verification of correctness and performance of random priority-based arbiters. FMCAD (2009)
Jason Baumgartner, Hari Mony, Viresh Paruthi, Robert Kanzelman, Geert Janssen
Scalable Sequential Equivalence Checking across Arbitrary Design Transformations . ICCD (2006)
Viresh Paruthi, Christian Jacobi, Kai Weber
Efficient Symbolic Simulation via Dynamic Scheduling, Don't Caring, and Case Splitting. CHARME (2005)
Christian Jacobi, Kai Weber, Viresh Paruthi, Jason Baumgartner
Automatic Formal Verification of Fused-Multiply-Add FPUs. DATE (2005)
Hari Mony, Jason Baumgartner, Viresh Paruthi, Robert Kanzelman
Exploiting suspected redundancy without proving it. DAC (2005)
Hari Mony, Jason Baumgartner, Viresh Paruthi, Robert Kanzelman, Andreas Kuehlmann
Scalable Automated Verification via Expert-System Guided Transformations. FMCAD (2004)
John M. Ludden, Wolfgang Roesner, Gerry M. Heiling, John R. Reysa, Jonathan R. Jackson, Bing-Lun Chu, Michael L. Behm, Jason Baumgartner, Richard D. Peterson, Jamee Abdulhafiz, William E. Bucy, John H. Klaus, Danny J. Klema, Tien N. Le, F. Danette Lewis, Philip E. Milling, Lawrence A. McConville, Bradley S. Nelson, Viresh Paruthi, Travis W. Pouarz, Audre D. Romonosky, Jeff Stuecheli, Kent D. Thompson, Dave W. Victor, Bruce Wile
Functional verification of the POWER4 microprocessor and POWER4 multiprocessor system. IBM J. Res. Dev. 46 (1) (2002)
Andreas Kuehlmann, Viresh Paruthi, Florian Krohm, Malay K. Ganai
Robust Boolean reasoning for equivalence checking and functional property verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21 (12) (2002)
Andreas Kuehlmann, Malay K. Ganai, Viresh Paruthi
Circuit-based Boolean Reasoning. DAC (2001)
Viresh Paruthi, Andreas Kuehlmann
Equivalence Checking Combining a Structural SAT-Solver, BDDs, and Simulation. ICCD (2000)
Viresh Paruthi, Nazanin Mansouri, Ranga Vemuri
Automatic data path abstraction for verification of large scale designs. ICCD (1998)