Ranga Vemuri

ORCID

Publication Activity (10 Years)

Years Active: 1978-2023
Publications (10 Years): 50

Top Venues

Publications

Aparajithan Nathamuni Venkatesan, Ram Venkat Narayanan, Kishore Pula, Sundarakumar Muthukumaran, Ranga Vemuri
Word-Level Structure Identification In FPGA Designs Using Cell Proximity Information. VLSID (2023)
Aparajithan Nathamuni Venkatesan, Ram Venkat Narayanan, Kishore Pula, Sundarakumar Muthukumaran, Ranga Vemuri
Word-Level Structure Identification In FPGA Designs Using Cell Proximity Information. CoRR (2023)
Juneet Kumar Meka, Ranga Vemuri
Attributed Graph Transformation for Generating Synthetic Benchmarks for Hardware Security. ISQED (2023)
Ram Venkat Narayanan, Aparajithan Nathamuni Venkatesan, Kishore Pula, Sundarakumar Muthukumaran, Ranga Vemuri
Reverse Engineering Word-Level Models from Look-Up Table Netlists. ISQED (2023)
Haimanti Chakraborty, Ranga Vemuri
Split Manufacturing Based Secure Hardware Design by BEOL Signal Selection In High Level Synthesis. MWSCAS (2023)
Ram Venkat Narayanan, Aparajithan Nathamuni Venkatesan, Kishore Pula, Sundarakumar Muthukumaran, Ranga Vemuri
Reverse Engineering Word-Level Models from Look-Up Table Netlists. CoRR (2023)
Sundarakumar Muthukumaran, Aparajithan Nathamuni Venkatesan, Kishore Pula, Ram Venkat Narayanan, Ranga Vemuri, John Marty Emmert
Reverse Engineering of RTL Controllers from Look-Up Table Netlists. ISVLSI (2023)
Nikhil Saxena, Ranga Vemuri
Hybrid Shielding: Amplifying the Power of Camouflaging and Logic Encryption. MWSCAS (2023)
Nikhil Saxena, Ranga Vemuri
Hybrid Shielding: Amplifying the Power of Camouflaging and Logic Encryption. IEEE Access 11 (2023)
Suriya Srinivasan, Ranga Vemuri
Mutation Analysis and Model Checking Guided Test Generation for SoC Run-Time Monitors. VLSID (2023)
Kishore Pula, Aparajithan Nathamuni Venkatesan, Ram Venkat Narayanan, Sundarakumar Muthukumaran, Ranga Vemuri, John Marty Emmert
RELUT-GNN: Reverse Engineering Data Path Elements From LUT Netlists Using Graph Neural Networks. MWSCAS (2023)
Padmaja Bhamidipati, Ranga Vemuri
ASPIRE: An Intermediate Representation for Abstract Security Policies. VLSID (2023)
Suriya Srinivasan, Ranga Vemuri
Model Checking Leveraged Error Localization for Complex RTL Designs. ICCD (2022)
Christopher Chuvalas, Ranga Vemuri
FPGA Acceleration of a Stochastic Local Search Portfolio Solver for Boolean Satisfiability. MWSCAS (2022)
Juneet Kumar Meka, Shrinidhi Venkatesh, Ranga Vemuri
Analysis of the Satisfiability Attack Against Logic Encryption Using Synthetic Benchmarks. iSES (2022)
Christopher Chuvalas, Ranga Vemuri
FPGA-Based Stochastic Local Search Satisfiability Solvers Exploiting High Bandwidth Memory. VLSI-SoC (2022)
Khitam M. Alatoun, Ranga Vemuri
Efficient Method for Timing-based Information Flow Verification in Hardware Designs. ACM Great Lakes Symposium on VLSI (2022)
Nikhil Saxena, Ranga Vemuri
ISPLock: A Hybrid Internal State Locking Method Using Polymorphic Gates. ISVLSI (2022)
Carla Purdy, John M. Emmert, Rashmi Jha, Ranga Vemuri
Educating the Next Generation of Cybersecurity Defenders at the University of Cincinnati. MWSCAS (2021)
David M. Luria, Ranga Vemuri
Logic Encryption for Resource Constrained Designs. IEEE Access 9 (2021)
Padmaja Bhamidipati, Shanmukha Murali Achyutha, Ranga Vemuri
Security Analysis of a System-on-Chip Using Assertion-Based Verification. MWSCAS (2021)
Khitam Alatoun, Bharath Shankaranarayanan, Shanmukha Murali Achyutha, Ranga Vemuri
SoC Trust Validation Using Assertion-Based Security Monitors. ISQED (2021)
Nikhil Saxena, Ram Venkat Narayanan, Juneet Kumar Meka, Ranga Vemuri
SRTLock: A Sensitivity Resilient Two-Tier Logic Encryption Scheme. iSES (2021)
Subashree Raja, Padmaja Bhamidipati, Xiaobang Liu, Ranga Vemuri
Security Capsules: An Architecture for Post-Silicon Security Assertion Validation for Systems-on-Chip. ISVLSI (2021)
Khitam M. Alatoun, Shanmukha Murali Achyutha, Ranga Vemuri
Efficient Methods for SoC Trust Validation Using Information Flow Verification. ICCD (2021)
Yasaswy Kasarabada, Ranga Vemuri
StateLock: State Transition Based Logic Locking for Sequential Circuits. VLSI Design (2020)
Yasaswy Kasarabada, Vaishali Muralidharan, Ranga Vemuri
SLED: Sequential Logic Encryption Using Dynamic Keys. MWSCAS (2020)
Suprajaa Tummala, Xiaobang Liu, Ranga Vemuri
Signal Selection Heuristics for Post-Silicon Validation. ISQED (2020)
Yasaswy Kasarabada, Suyuan Chen, Ranga Vemuri
On SAT-Based Attacks On Encrypted Sequential Logic Circuits. ISQED (2019)
Xiaobang Liu, Ranga Vemuri
Assertion Coverage Aware Trace Signal Selection in Post-Silicon Validation. ISQED (2019)
Harsh Vamja, Richa Agrawal, Ranga Vemuri
Non-Invasive Reverse Engineering of Finite State Machines Using Power Analysis and Boolean Satisfiability. MWSCAS (2019)
Richa Agrawal, Mike Borowczak, Ranga Vemuri
A State Encoding Methodology for Side-Channel Security vs. Power Trade-off Exploration. VLSI Design (2019)
Richa Agrawal, Ranga Vemuri, Mike Borowczak
A State Machine Encoding Methodology Against Power Analysis Attacks. J. Electron. Test. 35 (5) (2019)
Harsh Vamja, Richa Agrawal, Ranga Vemuri
Non-Invasive Reverse Engineering of Finite State Machines Using Power Analysis and Boolean Satisfiability. CoRR (2019)
Yasaswy Kasarabada, David M. Luria, Ranga Vemuri
Trust in IoT Devices: A Logic Encryption Perspective. IFIPIoT (2019)
Suyuan Chen, Ranga Vemuri
Exploiting Proximity Information in a Satisfiability Based Attack Against Split Manufactured Circuits. HOST (2019)
Yasaswy Kasarabada, Sudheer Ram Thulasi Raman, Ranga Vemuri
Deep State Encryption for Sequential Logic Circuits. ISVLSI (2019)
Mike Borowczak, Ranga Vemuri
Mitigating information leakage during critical communication using S*FSM. IET Comput. Digit. Tech. 13 (4) (2019)
Renuka Lokare, Ranga Vemuri
Progressive and secure performance unlocking for digital integrated circuits. ICCE (2018)
Xiaobang Liu, Ranga Vemuri
Combined Inference and Satisfiability Based Methods for Complete Signal Restoration in Post-Silicon Validation. VLSI Design (2018)
Ankita Manjunath Nayak, Ranga Vemuri
A secure tunable-precision architecture for image processing applications. ICCE (2018)
Pranav Dharmadhikari, Akhilesh Raju, Ranga Vemuri
Detection of Sequential Trojans in Embedded System Designs Without Scan Chains. ISVLSI (2018)
Richa Agrawal, Ranga Vemuri
On state encoding against power analysis attacks for finite state controllers. HOST (2018)
Suyuan Chen, Ranga Vemuri
On the Effectiveness of the Satisfiability Attack on Split Manufactured Circuits. VLSI-SoC (2018)
Xiaobang Liu, Ranga Vemuri
Fast Heuristics for Near-Optimal Signal Restoration in Post-Silicon Validation. ISVLSI (2018)
Suyuan Chen, Ranga Vemuri
Improving the Security of Split Manufacturing Using a Novel BEOL Signal Selection Method. ACM Great Lakes Symposium on VLSI (2018)
Suyuan Chen, Ranga Vemuri
Reverse Engineering of Split Manufactured Sequential Circuits Using Satisfiability Checking. ICCD (2018)
Xiaobang Liu, Ranga Vemuri
Effective Signal Restoration in Post-Silicon Validation. ICCD (2017)
Haibo Yi, Shaohua Tang, Ranga Vemuri
Fast Inversions in Small Finite Fields by Using Binary Trees. Comput. J. 59 (7) (2016)
Prabanjan Komari, Ranga Vemuri
A novel simulation based approach for trace signal selection in silicon debug. ICCD (2016)
Ramesh Nair, Ranga Vemuri
MITH-Dyn: A multi Vth dynamic logic design style using mixed mode FinFETs. SoCC (2014)
Mike Borowczak, Ranga Vemuri
Enabling Side Channel Secure FSMs in the Presence of Low Power Requirements. ISVLSI (2014)
Mike Borowczak, Ranga Vemuri
Secure controllers: Requirements of S*FSM. MWSCAS (2013)
Venkat Krishnan Balasubramanian, Hao Xu, Ranga Vemuri
Design automation flow for voltage adaptive optimum granularity LITHE for sequential circuits. SoCC (2013)
Annie Avakian, Natwar Agrawal, Ranga Vemuri
Reconfigurable Multicore Architecture for Dynamic Processor Reallocation. ARC (2012)
Lakshmi Narasimhan Ramakrishnan, Manoj Chakkaravarthy, Antarpreet Singh Manchanda, Mike Borowczak, Ranga Vemuri
SDMLp: On the use of complementary Pass transistor Logic for design of DPA resistant circuits. HOST (2012)
Aishwariya Pattabiraman, Annie Avakian, Ranga Vemuri
A Heterogeneous Cache Distribution with Reconfigurable Interconnect. IPDPS Workshops (2012)
Hao Xu, Ranga Vemuri, Wen-Ben Jone
Dynamic Characteristics of Power Gating During Mode Transition. IEEE Trans. Very Large Scale Integr. Syst. 19 (2) (2011)
Hao Xu, Wen-Ben Jone, Ranga Vemuri
Hopping With Temperature and Process Variation. IEEE Trans. Very Large Scale Integr. Syst. 19 (7) (2011)
Amayika Panda, Annie Avakian, Ranga Vemuri
Configurable workload generators for multicore architectures. SoCC (2011)
Hao Xu, Ranga Vemuri, Wen-Ben Jone
Current shaping and multi-thread activation for fast and reliable power mode transition in multicore designs. ICCAD (2010)
Hao Xu, Wen-Ben Jone, Ranga Vemuri
th Hopping for Aggressive Runtime Leakage Control. J. Low Power Electron. 6 (3) (2010)
Annie Avakian, Jon Nafziger, Amayika Panda, Ranga Vemuri
A reconfigurable architecture for multicore systems. IPDPS Workshops (2010)
Hao Xu, Wen-Ben Jone, Ranga Vemuri
Stretching the limit of microarchitectural level leakage control with Adaptive Light-Weight Vth Hopping. ICCAD (2010)
Hao Xu, Wen-Ben Jone, Ranga Vemuri
Novel Vth Hopping Techniques for Aggressive Runtime Leakage Control. VLSI Design (2010)
Jon Nafziger, Annie Avakian, Ranga Vemuri
A prediction-based, data Migration Algorithm for hybrid Architecture NoC systems. SoCC (2010)
Angan Das, Ranga Vemuri
Fuzzy Logic Based Guidance to Graph Grammar Framework for Automated Analog Circuit Design. VLSI Design (2009)
Shubhankar Basu, Balaji Kommineni, Ranga Vemuri
Variation-Aware Macromodeling and Synthesis of Analog Circuits Using Spline Center and Range Method and Dynamically Reduced Design Space. VLSI Design (2009)
Balasubramanian Sethuraman, Ranga Vemuri
A methodology for application-specific NoC architecture generation in a dynamic task structure environment. ACM Great Lakes Symposium on VLSI (2009)
Angan Das, Ranga Vemuri
A graph grammar based approach to automated multi-objective analog circuit design. DATE (2009)
Hao Xu, Ranga Vemuri, Wen-Ben Jone
Selective light Vth hopping (SLITH): Bridging the gap between runtime dynamic and leakage. DATE (2009)
Hao Xu, Ranga Vemuri, Wen-Ben Jone
Temporal and spatial idleness exploitation for optimal-grained leakage control. ICCAD (2009)
Romana Fernandes, Ranga Vemuri
Accurate estimation of vector dependent leakage power in the presence of process variations. ICCD (2009)
Almitra Pradhan, Ranga Vemuri
Efficient Synthesis of a Uniformly Spread Layout Aware Pareto Surface for Analog Circuits. VLSI Design (2009)
Hao Xu, Wen-Ben Jone, Ranga Vemuri
Accurate energy breakeven time estimation for run-time power gating. ICCAD (2008)
Srividhya Rammohan, Vijay Sundaresan, Ranga Vemuri
Reduced Complementary Dynamic and Differential Logic: A CMOS Logic Style for DPA-Resistant Secure IC Design. VLSI Design (2008)
Angan Das, Ranga Vemuri
Topology synthesis of analog circuits based on adaptively generated building blocks. DAC (2008)
Almitra Pradhan, Ranga Vemuri
Fast Analog Circuit Synthesis Using Sensitivity Based Near Neighbor Searches. DATE (2008)
Hao Xu, Ranga Vemuri, Wen-Ben Jone
Dynamic virtual ground voltage estimation for power gating. ISLPED (2008)
Shubhankar Basu, Balaji Kommineni, Ranga Vemuri
Mismatch Aware Analog Performance Macromodeling Using Spline Center and Range Regression on Adaptive Samples. VLSI Design (2008)
Hao Xu, Ranga Vemuri, Wen-Ben Jone
Run-time Active Leakage Reduction by power gating and reverse body biasing: An eNERGY vIEW. ICCD (2008)
Almitra Pradhan, Ranga Vemuri
A layout-aware analog synthesis procedure inclusive of dynamic module geometry selection. ACM Great Lakes Symposium on VLSI (2008)
Angan Das, Ranga Vemuri
ATLAS: An adaptively formed hierarchical cell library based analog synthesis framework. ISCAS (2008)
Shubhankar Basu, Balaji Kommineni, Ranga Vemuri
Variation Aware Spline Center and Range Modeling for Analog Circuit Performance. ISQED (2008)
Almitra Pradhan, Ranga Vemuri
On the Use of Hash Tables for Efficient Analog Circuit Synthesis. VLSI Design (2008)
Angan Das, Ranga Vemuri
A Self-learning Optimization Technique for Topology Design of Computer Networks. EvoWorkshops (2008)
Almitra Pradhan, Ranga Vemuri
Regression based circuit matrix models for accurate performance estimation of analog circuits. VLSI-SoC (2007)
Angan Das, Ranga Vemuri
GAPSYS: A GA-based Tool for Automated Passive Analog Circuit Synthesis. ISCAS (2007)
Shubhankar Basu, Priyanka Thakore, Ranga Vemuri
Process Variation Tolerant Standard Cell Library Development Using Reduced Dimension Statistical Modeling and Optimization Techniques. ISQED (2007)
Balasubramanian Sethuraman, Ranga Vemuri
A Force-directed Approach for Fast Generation of Efficient Multi-Port NoC Architectures. VLSI Design (2007)
Shubhankar Basu, Ranga Vemuri
Process Variation and NBTI Tolerant Standard Cells to Improve Parametric Yield and Lifetime of ICs. ISVLSI (2007)
Balasubramanian Sethuraman, Ranga Vemuri
Multicasting based topology generation and core mapping for a power efficient networks-on-chip. ISLPED (2007)
Almitra Pradhan, Ranga Vemuri
Accurate Performance Estimation using Circuit Matrix Models in Analog Circuit Synthesis. VLSI-SoC (Selected Papers) (2007)
Huiying Yang, Ranga Vemuri
Efficient Symbolic Sensitivity based Parasitic-Inclusive Optimization in Layout Aware Analog Circuit Synthesis. VLSI Design (2007)
Jawad Khan, Ranga Vemuri
An Iterative Algorithm for Battery-Aware Task Scheduling on Portable Computing Platforms CoRR (2007)
Balasubramanian Sethuraman, Ranga Vemuri
Power variations of multi-port routers in an application-specific NoC design : A case study. ICCD (2007)
Angan Das, Ranga Vemuri
An Automated Passive Analog Circuit Synthesis Framework using Genetic Algorithms. ISVLSI (2007)
Raoul F. Badaoui, Ranga Vemuri
Multi-Placement Structures for Fast and Optimized Placement in Analog Circuit Synthesis CoRR (2007)
Balaji Kommineni, Shubhankar Basu, Ranga Vemuri
A spline based regression technique on interval valued noisy data. ICMLA (2007)
Vijay Sundaresan, Srividhya Rammohan, Ranga Vemuri
Power invariant secure IC design methodology using reduced complementary dynamic and differential logic. VLSI-SoC (2007)

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Publication Activity (10 Years)

Top Topics

Top Venues

Ranga Vemuri