John M. Emmert

Publication Activity (10 Years)

Years Active: 1997-2022
Publications (10 Years): 5

Top Topics

Programmable Logic

Fpga Implementation

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

John M. Emmert, Anvesh Perumalla, Tristan J. Hudson, Luis Concha
THx2 Programmable Logic Block Architecture for Clockless Asynchronous FPGAs. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (7) (2022)
Aaron Ruen, Abhijeet Barua, Rashmi Jha, John M. Emmert
Fully BEOL-Compatible Switch Boxes Using RRAMs and Thin Film Transistors for Reconfigurable and Secure ICs. MWSCAS (2021)
John M. Emmert, Sara A. VanDewerker
EMC: Efficient Muller C-Element Implementation for High Bit-width Asynchronous Applications. MWSCAS (2021)
Carla Purdy, John M. Emmert, Rashmi Jha, Ranga Vemuri
Educating the Next Generation of Cybersecurity Defenders at the University of Cincinnati. MWSCAS (2021)
John M. Emmert, Anvesh Perumalla, Luis Concha
An Asynchronous FPGA THx2 Programmable Cell for Mitigating Side-Channel Attacks. MWSCAS (2020)
John M. Emmert, Charles E. Stroud, Miron Abramovici
Online Fault Tolerance for FPGA Logic Blocks. IEEE Trans. Very Large Scale Integr. Syst. 15 (2) (2007)
Jason A. Cheatham, John M. Emmert, Stanley Baumgart
A survey of fault tolerant methodologies for FPGAs. ACM Trans. Design Autom. Electr. Syst. 11 (2) (2006)
Miron Abramovici, Charles E. Stroud, John M. Emmert
Online BIST and BIST-based diagnosis of FPGA logic blocks. IEEE Trans. Very Large Scale Integr. Syst. 12 (12) (2004)
John M. Emmert, Jason A. Cheatham, Badhri Jagannathan, Sandeep Umarani
An FFT Approximation Technique Suitable for On-Chip Generation and Analysis of Sinusoidal Signals. DFT (2003)
John M. Emmert, Jason A. Cheatham, Badhri Jagannathan, Sandeep Umarani
A Monolithic Spectral BIST Technique for Control or Test of Analog or Mixed-Signal Circuits. DFT (2003)
John M. Emmert, Sandeep Lodha, Dinesh Bhatia
On Using Tabu Search for Design Automation of VLSI Systems. J. Heuristics 9 (1) (2003)
John M. Emmert, Stanley Baumgart, Pankaj Kataria, Andrew M. Taylor, Charles E. Stroud, Miron Abramovici
On-Line Fault Tolerance for FPGA Interconnect with Roving STARs. DFT (2001)
Miron Abramovici, Charles E. Stroud, Matthew Lashinsky, Jeremy Nall, John M. Emmert
On-Line BIST and Diagnosis of FPGA Interconnect Using Roving STARs. IOLTW (2001)
Miron Abramovici, John M. Emmert, Charles E. Stroud
Roving Stars: An Integrated Approach To On-Line Testing, Diagnosis, And Fault Tolerance For Fpgas In Adaptive Computing Systems. Evolvable Hardware (2001)
John M. Emmert, Dinesh K. Bhatia
Two-dimensional Placement Using Tabu Search. VLSI Design 2001 (1) (2001)
John M. Emmert, Jason A. Cheatham
On-Line Incremental Routing for Interconnect Fault Tolerance in FPGAs Minus the Router . DFT (2001)
John M. Emmert, Dinesh K. Bhatia
A Fault Tolerant Technique for FPGAs. J. Electron. Test. 16 (6) (2000)
Charles E. Stroud, John M. Emmert, John R. Bailey, Khushru S. Chhor, Dragan Nikolic
Bridging fault extraction from physical design data for manufacturing test development. ITC (2000)
John M. Emmert, Charles E. Stroud, Brandon Skaggs, Miron Abramovici
Dynamic Fault Tolerance in FPGAs via Partial Reconfiguration. FCCM (2000)
John M. Emmert, Charles E. Stroud, Jason A. Cheatham, Andrew M. Taylor, Pankaj Kataria, Miron Abramovici
Performance Penalty for Fault Tolerance in Roving STARs. FPL (2000)
Miron Abramovici, Charles E. Stroud, Brandon Skaggs, John M. Emmert
Improving On-Line BIST-Based Diagnosis for Roving STARs. IOLTW (2000)
John M. Emmert, Dinesh Bhatia
Fast timing driven placement using tabu search. ISCAS (1) (1999)
John M. Emmert, Dinesh Bhatia
A Methodology for Fast FPGA Floorplanning. FPGA (1999)
John M. Emmert, Dinesh Bhatia
Tabu Search: Ultra-Fast Placement for FPGAs. FPL (1999)
John M. Emmert, Akash Randhar, Dinesh Bhatia
Fast Floorplanning for FPGAs. FPL (1998)
John M. Emmert, Dinesh Bhatia
Partial reconfiguration of FPGA mapped designs with applications to fault tolerance and yield enhancement. FPL (1997)