Dinesh Bhatia

Publication Activity (10 Years)

Years Active: 1990-2023
Publications (10 Years): 17

Top Topics

Robust Estimator

Activation Patterns

Top Venues

Int. J. Medical Eng. Informatics

Publications

Dinesh Bhatia, Henrik Hesse
Enhancing Student Engagement in Engineering and Education Through Virtual Reality: A Survey-Based Analysis. TENCON (2023)
Ganesh Roy, Dinesh Bhatia, Subhasis Bhaumik
Feed Forward Neural Network BCI-based trajectory-controlled Lower-limb exoskeleton: a Biomechatronics Approach, 430-440. Int. J. Robotics Autom. 38 (6) (2023)
Pingakshya Goswami, Dinesh Bhatia
Application of Machine Learning in FPGA EDA Tool Development. IEEE Access 11 (2023)
Pingakshya Goswami, Benjamin Carrión Schäfer, Dinesh Bhatia
Machine learning based fast and accurate High Level Synthesis design space exploration: From graph to synthesis. Integr. 88 (2023)
Pingakshya Goswami, Masoud Shahshahani, Dinesh Bhatia
MLSBench: A Benchmark Set for Machine Learning based FPGA HLS Design Flows. LASCAS (2022)
Pingakshya Goswami, Dinesh Bhatia
Predicting Post-Route Quality of Results Estimates for HLS Designs using Machine Learning. ISQED (2022)
Pingakshya Goswami, Dinesh Bhatia
Predicting Post-Route Quality of Results Estimates for HLS Designs using Machine Learning. CoRR (2022)
Masoud Shahshahani, Dinesh Bhatia
PPA Based CNN Architecture Explorer. LASCAS (2022)
Pingakshya Goswami, Masoud Shahshahani, Dinesh Bhatia
Robust Estimation of FPGA Resources and Performance from CNN Models. VLSID (2022)
Masoud Shahshahani, Mohammad Sabri, Bahareh Khabbazan, Dinesh Bhatia
An Automated Tool for Implementing Deep Neural Networks on FPGA. VLSI Design (2021)
Masoud Shahshahani, Dinesh Bhatia
Resource and Performance Estimation for CNN Models using Machine Learning. ISVLSI (2021)
Gajendra Kumar Mourya, Dinesh Bhatia, Akash Handique
Empirical greedy machine-based automatic liver segmentation in CT images. IET Image Process. 14 (14) (2020)
Pingakshya Goswami, Dinesh Bhatia
Automated Floorplanning for Partially Reconfigurable Designs on Heterogenrous FPGAs. CoRR (2020)
Pingakshya Goswami, Masoud Shahshahani, Dinesh Bhatia
MLSBench: A Synthesizable Dataset of HLS Designs to Support ML Based Design Flows. FPGA (2020)
Athul Asokan Thulasi, Dinesh Bhatia, Poras T. Balsara, Shalini Prasad
Portable impedance measurement device for sweat based glucose detection. BSN (2017)
Pingakshya Goswami, Dinesh Bhatia
Floorplanning of Partially Reconfigurable Design on Heterogeneous FPGA (Abstract Only). FPGA (2016)
Shilpi Mathur, Manvinder Kaur, Dinesh Bhatia, Suresh Verma
Comparison of muscle activation patterns among healthy males and females during different lower limb movements. Int. J. Medical Eng. Informatics 8 (4) (2016)
Devender Singh, Manvinder Kaur, Dinesh Bhatia
Design of smart functional electric stimulator for physically challenged person. Int. J. Medical Eng. Informatics 6 (3) (2014)
Anu, Dinesh Bhatia
A smart door access system using finger print biometric system. Int. J. Medical Eng. Informatics 6 (3) (2014)
Abhishek Agarwal, Dinesh Bhatia
Quantitative measurement of carbon monoxide level in closed environment. Int. J. Medical Eng. Informatics 6 (3) (2014)
Dinesh Bhatia, A. L. Praveen Aroul
Antenna designs for wearable body sensor communication. PETRA (2013)
Dinesh Bhatia
Growth of neural engineering and neuro-mechanics in India: physically challenged looking towards a bright future. Int. J. Medical Eng. Informatics 5 (3) (2013)
Aruna Tyagi, Manoj Duhan, Dinesh Bhatia
Impact of communication technology on human brain activity: mobile phone vs. landline phone. Int. J. Medical Eng. Informatics 5 (1) (2013)
A. L. Praveen Aroul, Dinesh Bhatia
Study of performance and propagation characteristics of wire and planar structures around human body. EMBC (2011)
Shilpa Bhoj, Dinesh Bhatia
A dynamic temperature control simulation system for FPGAs. FPL (2008)
Shilpa Bhoj, Dinesh Bhatia
Early stage FPGA interconnect leakage power estimation. ICCD (2008)
A. L. Praveen Aroul, Achutan Manohar, Dinesh Bhatia, Leonardo Estevez
Power efficient multi-band contextual activity monitoring for assistive environments. PETRA (2008)
Shilpa Bhoj, Dinesh Bhatia
Thermal Modeling and Temperature Driven Placement for FPGAs. ISCAS (2007)
Shilpa Bhoj, Dinesh Bhatia
Pre-route Interconnect Capacitance and Power Estimation in FPGAs. FPL (2007)
Narayan Subramanian, Rajarshee P. Bharadwaj, Dinesh Bhatia
A leakage aware design methodology for power-gated programmable architectures. FPT (2006)
PariVallal Kannan, Dinesh Bhatia
Interconnect estimation for FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (8) (2006)
Sanjay Pratap Singh, Shilpa Bhoj, Dheera Balasubramanian, Tanvi Nagda, Dinesh Bhatia, Poras T. Balsara
Generic Network Interfaces for Plug and Play NoC Based Architecture. ARC (2006)
Rajan Konar, Rajarshee P. Bharadwaj, Dinesh Bhatia, Poras T. Balsara
Exploring Logic Block Granularity in Leakage Tolerant FPGA. VLSI Design (2006)
Mukesh Chugh, Dinesh Bhatia, Poras T. Balsara
Design and Implementation of Configurable W-CDMA Rake Receiver Architectures on FPGA. IPDPS (2005)
Manjunath Gangadhar, Dinesh Bhatia
FPGA based EBCOT architecture for JPEG 2000. Microprocess. Microsystems 29 (8-9) (2005)
Shankar Balachandran, Dinesh Bhatia
Timing Aware Interconnect Prediction Models for FPGAs. FPL (2005)
Shankar Balachandran, Dinesh Bhatia
A priori wirelength and interconnect estimation based on circuit characteristic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24 (7) (2005)
Rajarshee P. Bharadwaj, Rajan Konar, Dinesh Bhatia, Poras T. Balsara
FPGA Architecture for Standby Power Management. FPT (2005)
Rajarshee P. Bharadwaj, Rajan Konar, Poras T. Balsara, Dinesh Bhatia
Exploiting temporal idleness to reduce leakage power in programmable architectures. ASP-DAC (2005)
PariVallal Kannan, Shankar Balachandran, Dinesh Bhatia
On metrics for comparing interconnect estimation methods for FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 12 (4) (2004)
PariVallal Kannan, Dinesh Bhatia
Estimating Pre-Placement FPGA Interconnection Requirements. VLSI Design (2004)
PariVallal Kannan, Dinesh Bhatia
Interconnect Estimation for FPGAs under Timing Driven Domains. ICCD (2003)
Shankar Balachandran, Dinesh Bhatia
A-priori wirelength and interconnect estimation based on circuit characteristics. SLIP (2003)
Manjunath Gangadhar, Dinesh Bhatia
FPGA based EBCOT architecture for JPEG 2000. FPT (2003)
John M. Emmert, Sandeep Lodha, Dinesh Bhatia
On Using Tabu Search for Design Automation of VLSI Systems. J. Heuristics 9 (1) (2003)
PariVallal Kannan, Shankar Balachandran, Dinesh Bhatia
On metrics for comparing routability estimation methods for FPGAs. DAC (2002)
PariVallal Kannan, Shankar Balachandran, Dinesh Bhatia
Rapid and Reliable Routability Estimation for FPGAs. FPL (2002)
Shankar Balachandran, PariVallal Kannan, Dinesh Bhatia
On Routing Demand and Congestion Estimation for FPGAs. VLSI Design (2002)
PariVallal Kannan, Shankar Balachandran, Dinesh Bhatia
fGREP - Fast Generic Routing Demand Estimation for Placed FPGA Circuits. FPL (2001)
PariVallal Kannan, Dinesh Bhatia
Tightly Integrated Placement and Routing for FPGAs. FPL (2001)
Dinesh Bhatia, James Haralambides
Bounds, designs and layouts for multi-terminal FPIC architectures. Integr. 28 (2) (2000)
Dinesh Bhatia, James Haralambides
Resource requirements and layouts for field programmable interconnection chips. IEEE Trans. Very Large Scale Integr. Syst. 8 (3) (2000)
Karthikeya M. Gajjala Purna, Dinesh Bhatia
Temporal Partitioning and Scheduling Data Flow Graphs for Reconfigurable Computers. IEEE Trans. Computers 48 (6) (1999)
John M. Emmert, Dinesh Bhatia
Fast timing driven placement using tabu search. ISCAS (1) (1999)
John M. Emmert, Dinesh Bhatia
A Methodology for Fast FPGA Floorplanning. FPGA (1999)
John M. Emmert, Dinesh Bhatia
Tabu Search: Ultra-Fast Placement for FPGAs. FPL (1999)
Gregory Tumbush, Dinesh Bhatia
Clustering to improve bi-partition quality and run time. ISCAS (6) (1999)
Dinesh Bhatia, Kuldeep S. Simha, PariVallal Kannan
NEBULA: A Partially and Dynamically Reconfigurable Architecture. FPL (1999)
Natesan Venkateswaran, Dinesh Bhatia
Clock-skew constrained placement for row based designs. ICCD (1998)
Karthikeya M. Gajjala Purna, Dinesh Bhatia
Partitioning in time: a paradigm for reconfigurable computing. ICCD (1998)
Raghu Burra, Dinesh Bhatia
Timing Driven Multi-FPGA Board Partitioning. VLSI Design (1998)
Karthikeya M. Gajjala Purna, Dinesh Bhatia
Emulating Large Designs on Small Reconfigurable Hardware. International Workshop on Rapid System Prototyping (1998)
John M. Emmert, Akash Randhar, Dinesh Bhatia
Fast Floorplanning for FPGAs. FPL (1998)
Karthikeya M. Gajjala Purna, Dinesh Bhatia
Temporal Partitioning and Scheduling for Reconfigurable Computing. FCCM (1998)
Dinesh Bhatia, PariVallal Kannan, Kuldeep S. Simha, Karthikeya M. Gajjala Purna
REACT: Reactive Environment for Runtime Reconfiguration. FPL (1998)
Gregory Tumbush, Dinesh Bhatia
Partitioning Under Timing and Area Constraints. ICCD (1997)
Dinesh Bhatia
Reconfigurable Computing. VLSI Design (1997)
Jianzhong Shi, Akash Randhar, Dinesh Bhatia
Macro Block Based FPGA Floorplanning. VLSI Design (1997)
Natesan Venkateswaran, Anurag Gupta, Srinivas Katkoori, Dinesh Bhatia, Ranga Vemuri
A constructive method for data path area estimation during high-level VLSI synthesis. ASP-DAC (1997)
John M. Emmert, Dinesh Bhatia
Partial reconfiguration of FPGA mapped designs with applications to fault tolerance and yield enhancement. FPL (1997)
Jianzhong Shi, Dinesh Bhatia
Performance Driven Floorplanning for FPGA Based Designs. FPGA (1997)
Dinesh Bhatia
Field-Programmable Gate Arrays. VLSI Design 4 (4) (1996)
Dinesh Bhatia, Amit Chowdhary
A Multi-Terminal Net Router for Field-Programmable Gate Arrays. VLSI Design 4 (1) (1996)
Natesan Venkateswaran, Dinesh Bhatia
Clock-Skew Constrained Cell Placement. VLSI Design (1996)
Dinesh Bhatia, V. Shankar
Greedy Segmented Channel Router. VLSI Design 5 (1) (1996)
Doug Smith, Dinesh Bhatia
RACE: Reconfigurable and Adaptive Computing Environment. FPL (1996)
Vijayanand Sankarasubramanian, Dinesh Bhatia
Multiway Partitioner for High Performance FPGA Based Board Architecture. ICCD (1996)
Dinesh Bhatia, James Haralambides
Resource requirements for field programmable interconnection chips. VLSI Design (1995)
Dimitrios Kagaris, Spyros Tragoudas, Dinesh Bhatia
Pseudo-exhaustive built-in TPG for sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14 (9) (1995)
Amit Chowdhary, Dinesh Bhatia
Detailed Routing of Multi-Terminal Nets in FPGAs. VLSI Design (1994)
Dinesh Bhatia, Ramesh Rajagopalan, Srinivas Katkoori
Hierarchical Reconfiguration of VLSI/WSI Arrays. VLSI Design (1994)
Dinesh Bhatia, Amit Chowdhary, Spyros Tragoudas
Mathematical model for routability analysis of FPGAs. Great Lakes Symposium on VLSI (1994)
V. Shankar, Dinesh Bhatia
Generalized segmented channel routing. Great Lakes Symposium on VLSI (1994)
Dimitrios Kagaris, Spyros Tragoudas, Dinesh Bhatia
Pseudoexhaustive BIST for Sequential Circuits. ICCD (1993)
Dinesh Bhatia, Frank Thomson Leighton, Fillia Makedon, Carolyn Haibt Norton
Improved Algorithms for Routing on Two-Dimensional Grids. WG (1992)
Dinesh Bhatia, Frank Thomson Leighton, Fillia Makedon
Efficient Reconfiguration of WSI Arrays. ICSI (1990)