Poras T. Balsara

Publication Activity (10 Years)

Years Active: 1986-2024
Publications (10 Years): 12

Top Topics

Qr Decomposition

Frequency Response

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

IEEE Trans. Ind. Electron.

Publications

Hesam Nourmohamadi, Ghanshyamsinh Gohil, Poras T. Balsara
Intelligent Multi-Functional Fault Current Limiter. IEEE Trans. Smart Grid 15 (3) (2024)
Amisha Srivastava, Sneha Thakur, Abraham Peedikayil Kuruvila, Poras T. Balsara, Kanad Basu
Hardware-based Detection of Malicious Firmware Modification in Microgrids. VLSID (2024)
Vaibhav Uttam Pawaskar, Poras T. Balsara, Babak Fahimi, Ghanshyamsinh Gohil
Fully Distributed Control of Microgrids Using Multi-Agent Approach. IECON (2023)
G. Veera Bharath, Ghanshyamsinh Gohil, Poras T. Balsara
A new submodule structure with parallel capacitor connection in modular multilevel converters. ISCAS (2022)
Hesam Nourmohamadi, Mehran Sabahi, Poras T. Balsara, Ebrahim Babaei, Seyed Hossein Hosseini, Amir Fakhim-Babaei
New Concept for Fault Current Limiter With Voltage Restoration Capability. IEEE Trans. Ind. Electron. 67 (12) (2020)
Vikas V. Paduvalli, R. J. Taylor, Louis R. Hunt, Poras T. Balsara
Mitigation of Positive Zero Effect on Nonminimum Phase Boost DC-DC Converters in CCM. IEEE Trans. Ind. Electron. 65 (5) (2018)
Essam S. Atalla, Frank Zhang, Poras T. Balsara, Abdellatif Bellaouar, Seydou Ba, Kamran Kiasaleh
Time-Domain Analysis of Passive Mixer Impedance: A Switched-Capacitor Approach. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2017)
Vikas V. Paduvalli, R. J. Taylor, Poras T. Balsara
Analysis of Zeros in a Boost DC-DC Converter: State Diagram Approach. IEEE Trans. Circuits Syst. II Express Briefs (5) (2017)
Athul Asokan Thulasi, Dinesh Bhatia, Poras T. Balsara, Shalini Prasad
Portable impedance measurement device for sweat based glucose detection. BSN (2017)
Sameer Arora, Poras T. Balsara, Dinesh K. Bhatia
Effect of sampling time and sampling instant on the frequency response of a boost converter. IECON (2016)
Imran Bashir, Robert Bogdan Staszewski, Poras T. Balsara
A Digitally Controlled Injection-Locked Oscillator With Fine Frequency Resolution. IEEE J. Solid State Circuits 51 (6) (2016)
Imran Bashir, Robert Bogdan Staszewski, Oren E. Eliezer, Poras T. Balsara
A Wideband Digital-to-Frequency Converter with Built-In Mechanism for Self-Interference Mitigation. J. Electron. Test. 32 (4) (2016)
Sujan K. Manohar, L. R. Hunt, Poras T. Balsara, Dinesh K. Bhatia, Vikas V. Paduvalli
Minimum Phase Wide Output Range Digitally Controlled SIDO Boost Converter. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2015)
Sankalp Modi, Poras T. Balsara, Oren E. Eliezer
Envelope tracking using transient waveform switching shaping supply modulation. Int. J. Circuit Theory Appl. 43 (5) (2015)
Aditya Awasthi, Rohit Guttal, Naofal Al-Dhahir, Poras T. Balsara
Complex QR Decomposition Using Fast Plane Rotations for MIMO Applications. IEEE Commun. Lett. 18 (10) (2014)
Essam S. Atalla, Abdellatif Bellaouar, Poras T. Balsara
Novel analysis of passive mixer output impedance using switched-capacitor techniques. MWSCAS (2013)
Sujan K. Manohar, Poras T. Balsara
94.6% peak efficiency DCM buck converter with fast adaptive dead-time control. ESSCIRC (2013)
Essam S. Atalla, Abdellatif Bellaouar, Poras T. Balsara
IIP2 requirements in 4G LTE handset receivers. MWSCAS (2013)
Essam S. Atalla, Frank Zhang, Abdellatif Bellaouar, Poras T. Balsara
Estimation of passive mixer output bandwidth using switched-capacitor techniques. CICC (2013)
Sujan K. Manohar, Ramakrishnan Venkatasubramanian, Poras T. Balsara
Hybrid NEMS-CMOS DC-DC Converter for Improved Area and Power Efficiency. VLSI Design (2012)
Sujan K. Manohar, Vinod K. Somasundar, Ramakrishnan Venkatasubramanian, Poras T. Balsara
Bidirectional Single-Supply Level Shifter with Wide Voltage Range for Efficient Power Management. VLSI Design (2012)
Aditya Awasthi, Naofal Al-Dhahir, Oren E. Eliezer, Poras T. Balsara
Alien crosstalk mitigation in vectored DSL systems for backhaul applications. ICC (2012)
Ioannis L. Syllaios, Poras T. Balsara
Linear Time-Variant Modeling and Analysis of All-Digital Phase-Locked Loops. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2012)
Imran Bashir, Robert Bogdan Staszewski, Oren E. Eliezer, Bhaskar Banerjee, Poras T. Balsara
A Novel Approach for Mitigation of RF Oscillator Pulling in a Polar Transmitter. IEEE J. Solid State Circuits 46 (2) (2011)
Ioannis L. Syllaios, Poras T. Balsara
Multi-clock domain analysis and modeling of all-digital frequency synthesizers. ISCAS (2011)
Ramakrishnan Venkatasubramanian, Sujan K. Manohar, Poras T. Balsara
Improving performance of NEM relay logic circuits using integrated charge-boosting flip flop. NANOARCH (2011)
Venkata K. Kidambi Srinivasan, Chitranjan K. Singh, Poras T. Balsara
A Generic Scalable Architecture for Min-Sum/Offset-Min-Sum Unit for Irregular/Regular LDPC Decoder. IEEE Trans. Very Large Scale Integr. Syst. 18 (9) (2010)
Mangesh K. Kunchamwar, Durga P. Prasad, Pawan Hegde, Poras T. Balsara, Rama Sangireddy
Application Specific Instruction Accelerator for Multistandard Viterbi and Turbo Decoding. ICPP Workshops (2010)
Ioannis L. Syllaios, Poras T. Balsara, Robert Bogdan Staszewski
Recombination of Envelope and Phase Paths in Wideband Polar Transmitters. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2010)
Jaimin Mehta, Vasile Zoicas, Oren E. Eliezer, Robert Bogdan Staszewski, Sameh Rezeq, Mitch Entezari, Poras T. Balsara
An Efficient Linearization Scheme for a Digital Polar EDGE Transmitter. IEEE Trans. Circuits Syst. II Express Briefs (3) (2010)
Lei Wang, Pawankumar Hegde, Vishal Nawathe, Roman Staszewski, Poras T. Balsara, Vojin G. Oklobdzija
Design of a link-controller architecture for multiple serial link protocols. SoCC (2010)
Oren Eytan Eliezer, Robert Bogdan Staszewski, Imran Bashir, Sumeer Bhatara, Poras T. Balsara
A Phase Domain Approach for Mitigation of Self-Interference in Wireless Transceivers. IEEE J. Solid State Circuits 44 (5) (2009)
Viral K. Parikh, Poras T. Balsara, Oren E. Eliezer
All Digital-Quadrature-Modulator Based Wideband Wireless Transmitters. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2009)
Imtinan Elahi, Khurram Muhammad, Poras T. Balsara
Parallel Correction and Adaptation Engines for I/Q Mismatch Compensation. IEEE Trans. Circuits Syst. II Express Briefs (1) (2009)
Ioannis L. Syllaios, Robert Bogdan Staszewski, Poras T. Balsara
Time-Domain Modeling of an RF All-Digital PLL. IEEE Trans. Circuits Syst. II Express Briefs (6) (2008)
Chitranjan K. Singh, Naofal Al-Dhahir, Poras T. Balsara
Effect of Word-length Precision on the Performance of MIMO Systems. ISCAS (2007)
Viral K. Parikh, Poras T. Balsara, Oren E. Eliezer, Jaimin Mehta
A Low Area and Low Power Digital Band-Pass Sigma-Delta Modulator for Wireless Transmitters. ISCAS (2007)
Viral K. Parikh, Poras T. Balsara, Oren E. Eliezer, Jaimin Mehta
A Low Power and Low Quantization Noise Digital Sigma-Delta Modulator for Wireless Transmitters. ISCAS (2007)
Ioannis L. Syllaios, Poras T. Balsara, Robert Bogdan Staszewski
On the Reconfigurability of All-Digital Phase-Locked Loops for Software Defined Radios. PIMRC (2007)
Robert Bogdan Staszewski, Poras T. Balsara
All-Digital PLL With Ultra Fast Settling. IEEE Trans. Circuits Syst. II Express Briefs (2) (2007)
Raghunath Cherukuri, Poras T. Balsara
Iterative (TURBO) IQ Imbalance Estimation and Correction in BICM-ID for Flat Fading Channels. VTC Fall (2007)
Chitranjan K. Singh, Sushma Honnavara Prasad, Poras T. Balsara
VLSI Architecture for Matrix Inversion using Modified Gram-Schmidt based QR Decomposition. VLSI Design (2007)
Ioannis L. Syllaios, Poras T. Balsara, Robert Bogdan Staszewski
Time-Domain Modeling of a Phase-Domain All-Digital Phase-Locked Loop for RF Applications. CICC (2007)
Robert Bogdan Staszewski, Sudheer K. Vemulapalli, Prasant Vallur, John L. Wallberg, Poras T. Balsara
1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs (3) (2006)
Imtinan Elahi, Khurram Muhammad, Poras T. Balsara
IIP2 and DC Offsets in the Presence of Leakage at LO Frequency. IEEE Trans. Circuits Syst. II Express Briefs (8) (2006)
Sanjay Pratap Singh, Shilpa Bhoj, Dheera Balasubramanian, Tanvi Nagda, Dinesh Bhatia, Poras T. Balsara
Generic Network Interfaces for Plug and Play NoC Based Architecture. ARC (2006)
Rajan Konar, Rajarshee P. Bharadwaj, Dinesh Bhatia, Poras T. Balsara
Exploring Logic Block Granularity in Leakage Tolerant FPGA. VLSI Design (2006)
Ioannis L. Syllaios, Poras T. Balsara, Oren E. Eliezer
A generalized signal reconstruction method for designing interpolation filters. ISCAS (2006)
V. Ramakrishnan, Poras T. Balsara
A Wide-Range, High-Resolution, Compact CMOS, Time to Digital Converter. VLSI Design (2006)
Mehrdad Nourani, Deepak S. Vijayasarathi, Poras T. Balsara
Reconfigurable CAM Architecture for Network Search Engines. ICCD (2006)
Imtinan Elahi, Khurram Muhammad, Poras T. Balsara
I/Q mismatch compensation using adaptive decorrelation in a low-IF receiver in 90-nm CMOS process. IEEE J. Solid State Circuits 41 (2) (2006)
Ramaprasath Vilangudipitchai, Poras T. Balsara
Power Switch Network Design for MTCMOS. VLSI Design (2005)
Mukesh Chugh, Dinesh Bhatia, Poras T. Balsara
Design and Implementation of Configurable W-CDMA Rake Receiver Architectures on FPGA. IPDPS (2005)
Robert Bogdan Staszewski, Dirk Leipold, Poras T. Balsara
Direct frequency modulation of an ADPLL for bluetooth/GSM with injection pulling elimination. IEEE Trans. Circuits Syst. II Express Briefs (6) (2005)
Deepak S. Vijayasarathi, Mehrdad Nourani, Mohammad J. Akhbarizadeh, Poras T. Balsara
Ripple-Precharge TCAM A Low-Power Solution for Network Search Engines. ICCD (2005)
Rajarshee P. Bharadwaj, Rajan Konar, Dinesh Bhatia, Poras T. Balsara
FPGA Architecture for Standby Power Management. FPT (2005)
Robert Bogdan Staszewski, Roman Staszewski, John L. Wallberg, Tom Jung, Chih-Ming Hung, Jinseok Koh, Dirk Leipold, Kenneth Maggio, Poras T. Balsara
SoC with an integrated DSP and a 2.4-GHz RF transmitter. IEEE Trans. Very Large Scale Integr. Syst. 13 (11) (2005)
Rajarshee P. Bharadwaj, Rajan Konar, Poras T. Balsara, Dinesh Bhatia
Exploiting temporal idleness to reduce leakage power in programmable architectures. ASP-DAC (2005)
Robert Bogdan Staszewski, Poras T. Balsara
Phase-domain all-digital phase-locked loop. IEEE Trans. Circuits Syst. II Express Briefs (3) (2005)
Robert Bogdan Staszewski, Chan Fernando, Poras T. Balsara
Event-driven Simulation and modeling of phase noise of an RF oscillator. IEEE Trans. Circuits Syst. I Regul. Pap. (4) (2005)
Robert Bogdan Staszewski, Roman Staszewski, Poras T. Balsara
VHDL Simulation and Modeling of an All-Digital RF Transmitter. IWSOC (2005)
N. S. Nagaraj, William R. Hunter, Poras T. Balsara, Cyrus D. Cantrell
The Impact of Inductance on Transients Affecting Gate Oxide Reliability. VLSI Design (2005)
Robert Bogdan Staszewski, Chan Fernando, Poras T. Balsara
Event-driven simulation and modeling of an RF oscillator. ISCAS (4) (2004)
N. S. Nagaraj, Tom Bonifield, Abha Singh, Roger Griesmer, Poras T. Balsara
Interconnect Modeling for Copper/Low-k Technologies. VLSI Design (2004)
Mohammad J. Akhbarizadeh, Mehrdad Nourani, Deepak S. Vijayasarathi, Poras T. Balsara
PCAM: A Ternary CAM Optimized for Longest Prefix Matching Tasks. ICCD (2004)
Robert Bogdan Staszewski, Khurram Muhammad, Dirk Leipold, Chih-Ming Hung, Yo-Chuol Ho, John L. Wallberg, Chan Fernando, Ken Maggio, Roman Staszewski, Tom Jung, Jinseok Koh, Soji John, Irene Yuanying Deng, Vivek Sarda, Oscar Moreira-Tamayo, Valerian Mayega, Ran Katz, Ofer Friedman, Oren Eytan Eliezer, Elida de-Obaldia, Poras T. Balsara
All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS. IEEE J. Solid State Circuits 39 (12) (2004)
N. S. Nagaraj, Tom Bonifield, Abha Singh, Frank Cano, Usha Narasimha, Mak Kulkarni, Poras T. Balsara, Cyrus D. Cantrell
Benchmarks for Interconnect Parasitic Resistance and Capacitance. ISQED (2003)
Robert Bogdan Staszewski, Dirk Leipold, Khurram Muhammad, Poras T. Balsara
Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS Process. IEEE Trans. Circuits Syst. II Express Briefs 50 (11) (2003)
Robert Bogdan Staszewski, Dirk Leipold, Poras T. Balsara
Just-in-time gain estimation of an RF digitally-controlled oscillator for digital direct frequency modulation. IEEE Trans. Circuits Syst. II Express Briefs 50 (11) (2003)
N. S. Nagaraj, Poras T. Balsara, Cyrus D. Cantrell
Embedded Tutorial: Modeling Parasitic Coupling Effects in Reliability Verification. VLSI Design (2002)
Nagaraj Ns, Poras T. Balsara, Cyrus D. Cantrell
Crosstalk Noise Verification in Digital Designs with Interconnect Process Variations. VLSI Design (2001)
Khurram Muhammad, Robert Bogdan Staszewski, Poras T. Balsara
Speed, power, area, and latency tradeoffs in adaptive FIR filtering for PRML read channels. IEEE Trans. Very Large Scale Integr. Syst. 9 (1) (2001)
Khurram Muhammad, Robert Bogdan Staszewski, Poras T. Balsara
Challenges in integrated CMOS transceivers for short distance wireless. ACM Great Lakes Symposium on VLSI (2001)
Robert Bogdan Staszewski, Khurram Muhammad, Poras T. Balsara
A 550-MSample/s 8-Tap FIR digital filter for magnetic recording read channels. IEEE J. Solid State Circuits 35 (8) (2000)
Khurram Muhammad, Robert Bogdan Staszewski, Poras T. Balsara
Low power techniques and design tradeoffs in adaptive FIR filtering for PRML read channels. ISLPED (2000)
Kamlesh Rath, Sirisha Tangirala, Patrick Friel, Poras T. Balsara, Jose Flores, John P. Wadley
Reconfigurable Array Media Processor (RAMP). FCCM (2000)
Uming Ko, Poras T. Balsara
High-performance energy-efficient D-flip-flop circuits. IEEE Trans. Very Large Scale Integr. Syst. 8 (1) (2000)
Shivaling S. Mahant-Shetti, Poras T. Balsara, Carl Lemonds
High performance low power array multiplier using temporal tiling. IEEE Trans. Very Large Scale Integr. Syst. 7 (1) (1999)
Nagaraj Ns, Poras T. Balsara, Cyrus D. Cantrell
Mini-Tutorial: Bridging the Gap between TCAD and ECAD Methodologies in Deep Sub-Micron Interconnect Extraction and Analysis. VLSI Design (1999)
Uming Ko, Poras T. Balsara, Ashwini K. Nanda
Energy optimization of multilevel cache architectures for RISC and CISC processors. IEEE Trans. Very Large Scale Integr. Syst. 6 (2) (1998)
Sharat Prasad, Kamran Kiasaleh, Poras T. Balsara
LAPLUS: An Efficient, Effective and Stable Switch Algorithm for Flow Control of the Available Bit Rate ATM Service. INFOCOM (1998)
Pius Ng, Poras T. Balsara, Don Steiss
Performance of CMOS differential circuits. IEEE J. Solid State Circuits 31 (6) (1996)
Shivaling S. Mahant-Shetti, Carl Lemonds, Poras T. Balsara
Leap frog multiplier. ISLPED (1996)
Uming Ko, Anthony M. Hill, Poras T. Balsara
Design techniques for high performance, energy efficient control logic. ISLPED (1996)
M. Agarwala, Poras T. Balsara
An architecture for a DSP field-programmable gate array. IEEE Trans. Very Large Scale Integr. Syst. 3 (1) (1995)
Uming Ko, Poras T. Balsara, Ashwini K. Nanda
Energy optimization of multi-level processor cache architectures. ISLPD (1995)
Whoi-Yul Kim, Poras T. Balsara, David T. Harper III, Jon Wong Park
Hierarchy embedded differential image for progressive transmission using lossless compression. IEEE Trans. Circuits Syst. Video Technol. 5 (1) (1995)
Uming Ko, Poras T. Balsara
Short-circuit power driven gate sizing technique for reducing power dissipation. IEEE Trans. Very Large Scale Integr. Syst. 3 (3) (1995)
Arun Vaidyanathan, Eric M. Dowling, Poras T. Balsara
Design and implementation of a multi-microprocessor architecture for image processing. Microprocess. Microsystems 16 (6) (1992)
Poras T. Balsara, Mary Jane Irwin
Intermediate-level vision tasks on a memory array architecture. Mach. Vis. Appl. 6 (1) (1992)
Poras T. Balsara, Robert Michael Owens, Mary Jane Irwin
Digit Serial Multipliers. J. Parallel Distributed Comput. 11 (2) (1991)
Poras T. Balsara, Mary Jane Irwin
Image processing on a memory array architecture. J. VLSI Signal Process. 2 (4) (1991)
Poras T. Balsara, Robert Michael Owens
Systolic & semi-systolic digit serial multipliers. IEEE Symposium on Computer Arithmetic (1987)
Shishpal Rawat, Poras T. Balsara, Mary Jane Irwin, Tom Mackowiak
Design and implementation of real time video processor. ICASSP (1986)