Short-circuit power driven gate sizing technique for reducing power dissipation.

Uming Ko Poras T. Balsara

Published in: IEEE Trans. Very Large Scale Integr. Syst. (1995)

Keyphrases

short circuit
power dissipation
power consumption
power reduction
cmos technology
low power
nm technology
chip design
logic circuits
digital signal processing
thin film
low cost
real time
finite state machines
power losses
flip flops
design methodology
neural nets
pattern matching
signal processing
case study