Ashwini K. Nanda

Publication Activity (10 Years)

Years Active: 1991-2007
Publications (10 Years): 0

Publications

H. Peter Hofstee, Ashwini K. Nanda, John J. Ritsko
Preface. IBM J. Res. Dev. 51 (5) (2007)
Ashwini K. Nanda, J. Randal Moulic, Robert E. Hanson, Gottfried Goldrian, Michael N. Day, Bruce D. D'Amora, Sreeni Kesavarapu
Cell/B.E. blades: Building blocks for scalable, real-time, interactive, and digital media servers. IBM J. Res. Dev. 51 (5) (2007)
Yang Liu, Holger Jones, Sheila Vaidya, Michael Perrone, Borivoj Tydlitát, Ashwini K. Nanda
Speech recognition systems on the Cell Broadband Engine processor. IBM J. Res. Dev. 51 (5) (2007)
Bruce D'Amora, Ashwini K. Nanda, Karen A. Magerlein, Atman Binstock, Bernard Yee
High-performance server systems and the next generation of online games. IBM Syst. J. 45 (1) (2006)
Kimberly Keeton, Russell M. Clapp, Ashwini K. Nanda
Guest Editors' Introduction: Evaluating Servers with Commercial Workloads. Computer 36 (2) (2003)
Michel Dubois, Jaeheon Jeong, Ashwini K. Nanda
Shared cache architectures for decision support systems. Perform. Evaluation 49 (1/4) (2002)
Ashwini K. Nanda, Anthony-Trung Nguyen, Maged M. Michael, Douglas J. Joseph
High-throughout coherence control and hardware messaging in Everest. IBM J. Res. Dev. 45 (2) (2001)
Yiming Hu, Ashwini K. Nanda, Qing Yang
Measurement, Analysis and Performance Improvement of the Apache Web Server. Int. J. Comput. Their Appl. 8 (4) (2001)
Ravi R. Iyer, Laxmi N. Bhuyan, Ashwini K. Nanda
Using Switch Directories to Speed Up Cache-to-Cache Transfers in CC-NUMA Multiprocessors. IPDPS (2000)
Ashwini K. Nanda, Anthony-Trung Nguyen, Maged M. Michael, Douglas J. Joseph
High-Throughput Coherence Controllers. HPCA (2000)
Ashwini K. Nanda, Kwok-Ken Mak, Krishnan Sugavanam, Ramendra K. Sahoo, Vijayaraghavan Soundararajan, T. Basil Smith
MemorIES: A Programmable, Real-Time Hardware Emulation Tool for Multiprocessor Server Design. ASPLOS (2000)
Maged M. Michael, Ashwini K. Nanda, Beng-Hong Lim
Coherence Controller Architectures for Scalable Shared-Memory Multiprocessors. IEEE Trans. Computers 48 (2) (1999)
Russell M. Clapp, Ashwini K. Nanda, Josep Torrellas
Second Workshop on Computer Architecture Evaluation Using Commercial Workloads. HPCA (1999)
Maged M. Michael, Ashwini K. Nanda
Design and Performance of Directory Caches for Scalable Shared Memory Multiprocessors. HPCA (1999)
Yiming Hu, Ashwini K. Nanda, Qing Yang
Measurement, analysis and performance improvement of the Apache Web server. IPCCC (1999)
Ashwini K. Nanda, Yiming Hu, Moriyoshi Ohara, Caroline Benveniste, Mark Giampapa, Maged M. Michael
The Design of COMPASS: An Execution Driven Simulator for Commercial Applications Running on Shared Memory Multiprocessors. IPPS/SPDP (1998)
Ashwini K. Nanda, James O. Bondi, Simonjit Dutta
The Misprediction Recovery Cache. Int. J. Parallel Program. 26 (4) (1998)
Uming Ko, Poras T. Balsara, Ashwini K. Nanda
Energy optimization of multilevel cache architectures for RISC and CISC processors. IEEE Trans. Very Large Scale Integr. Syst. 6 (2) (1998)
Maged M. Michael, Ashwini K. Nanda, Beng-Hong Lim, Michael L. Scott
Coherence Controller Architectures for SMP-Based CC-NUMA Multiprocessors. ISCA (1997)
Anthony-Trung Nguyen, Pradip Bose, Kattamuri Ekanadham, Ashwini K. Nanda, Maged M. Michael
Accuracy and Speedup of Parallel Trace-Driven Architectural Simulation. IPPS (1997)
Laxmi N. Bhuyan, Ravi R. Iyer, Tahsin Askar, Ashwini K. Nanda, Mohan Kumar
Performance of Multistage Bus Networks for a Distributed Shared Memory Multiprocessor. IEEE Trans. Parallel Distributed Syst. 8 (1) (1997)
James O. Bondi, Ashwini K. Nanda, Simonjit Dutta
Integrating a Misprediction Recovery Cache (MRC) into a Superscalar Pipeline. MICRO (1996)
Uming Ko, Poras T. Balsara, Ashwini K. Nanda
Energy optimization of multi-level processor cache architectures. ISLPD (1995)
Laxmi N. Bhuyan, Ashwini K. Nanda, Tahsin Askar
Performance and Reliability of the Multistage Bus Network. ICPP (1) (1994)
Ashwini K. Nanda, Laxmi N. Bhuyan
Efficient Mapping of Applications on Cache Based Multiprocessors. J. Parallel Distributed Comput. 19 (3) (1993)
Ashwini K. Nanda, Laxmi N. Bhuyan
Design and Analysis of Cache Coherent Multistage Interconnection Networks. IEEE Trans. Computers 42 (4) (1993)
Ashwini K. Nanda, Doug DeGroot, Daniel L. Stenger
Scheduling Directed Task Graphs on Multiprocessors Using Simulated Annealing. ICDCS (1992)
Ashwini K. Nanda, Hong Jiang
Analysis of Directory Based Cache Coherence Schemes with Multistage Networks. ACM Conference on Computer Science (1992)
Ashwini K. Nanda, Laxmi N. Bhuyan
A Formal Specification and Verification Technique for Cache Coherence Protocols. ICPP (1) (1992)
Ashwini K. Nanda, Laxmi N. Bhuyan
Mapping Applications onto a Cache Coherent Multiprocessor. SC (1992)
Laxmi N. Bhuyan, Ashwini K. Nanda
Multistage bus network (MBN): an interconnection network for cache coherent multiprocessors. SPDP (1991)