Energy optimization of multilevel cache architectures for RISC and CISC processors.
Uming KoPoras T. BalsaraAshwini K. NandaPublished in: IEEE Trans. Very Large Scale Integr. Syst. (1998)
Keyphrases
- memory hierarchy
- instruction set
- embedded processors
- optimization problems
- optimization algorithm
- parallel architectures
- memory subsystem
- main memory
- application specific
- energy consumption
- parallel algorithm
- optimization method
- database systems
- computer architecture
- energy minimization
- memory access
- query processing