Michel Dubois

Publication Activity (10 Years)

Years Active: 1981-2020
Publications (10 Years): 4

Top Venues

IEEE Trans. Computers

ACM Trans. Archit. Code Optim.

SAMOS

IEEE Comput. Archit. Lett.

Publications

Sang Wook Stephen Do, Michel Dubois
Transaction-Based Core Reliability. IPDPS (2020)
Sang Wook Stephen Do, Michel Dubois
Core Reliability: Leveraging Hardware Transactional Memory. IEEE Comput. Archit. Lett. 17 (2) (2018)
Mehrtash Manoochehri, Michel Dubois
Accurate Model for Application Failure Due to Transient Faults in Caches. IEEE Trans. Computers 65 (8) (2016)
Sang Wook Stephen Do, Michel Dubois
Power Efficient Hardware Transactional Memory: Dynamic Issue of Transactions. ACM Trans. Archit. Code Optim. 13 (1) (2016)
Mehrtash Manoochehri, Michel Dubois
Chip-independent Error Correction in main memories. SAMOS (2015)
Jinho Suh, Chieh-Ting Huang, Michel Dubois
Dynamic MIPS Rate Stabilization for Complex Processors. ACM Trans. Archit. Code Optim. 12 (1) (2015)
Mehrtash Manoochehri, Murali Annavaram, Michel Dubois
Extremely Low Cost Error Protection with Correctable Parity Protected Cache. IEEE Trans. Computers 63 (10) (2014)
Waleed Dweik, Murali Annavaram, Michel Dubois
Reliability-Aware Exceptions: Tolerating intermittent faults in microprocessor array structures. DATE (2014)
Jinho Suh, Murali Annavaram, Michel Dubois
PHYS: Profiled-HYbrid Sampling for soft error reliability benchmarking. DSN (2013)
Jinho Suh, Murali Annavaram, Michel Dubois
MACAU: A Markov model for reliability evaluations of caches under Single-bit and Multi-bit Upsets. HPCA (2012)
Mehrtash Manoochehri, Murali Annavaram, Michel Dubois
CPPC: correctable parity protected cache. ISCA (2011)
Jinho Suh, Mehrtash Manoochehri, Murali Annavaram, Michel Dubois
Soft error benchmarking of L2 caches with PARMA. SIGMETRICS (2011)
Jianwei Chen, Lakshmi Kumar Dabbiru, Daniel Wong, Murali Annavaram, Michel Dubois
Adaptive and Speculative Slack Simulations of CMPs on CMPs. MICRO (2010)
Jianwei Chen, Murali Annavaram, Michel Dubois
Exploiting Simulation Slack to Improve Parallel Simulation Speed. ICPP (2009)
Jianwei Chen, Murali Annavaram, Michel Dubois
SlackSim: a platform for parallel simulations of CMPs on CMPs. SIGMETRICS Perform. Evaluation Rev. 37 (2) (2009)
Adrian Moga, Michel Dubois
A comparative evaluation of hybrid distributed shared-memory systems. J. Syst. Archit. 55 (1) (2009)
Jianwei Chen, Murali Annavaram, Michel Dubois
SlackSim: a platform for parallel simulations of CMPs on CMPs. SIGARCH Comput. Archit. News 37 (2) (2009)
Woojin Choi, Seok-Jun Park, Michel Dubois
Accurate Instruction Pre-scheduling in Dynamically Scheduled Processors. Trans. High Perform. Embed. Archit. Compil. 2 (2009)
Jinho Suh, Michel Dubois
Dynamic MIPS rate stabilization in out-of-order processors. ISCA (2009)
Jaeheon Jeong, Per Stenström, Michel Dubois
Simple Penalty-Sensitive Cache Replacement Policies. J. Instr. Level Parallelism 10 (2008)
Xiaogang Qiu, Michel Dubois
The Synonym Lookaside Buffer: A Solution to the Synonym Problem in Virtual Caches. IEEE Trans. Computers 57 (12) (2008)
Michel Dubois, Hyunyoung Lee
STAMP: A universal algorithmic model for next-generation multithreaded machines and systems. IPDPS (2008)
Jianwei Chen, Michel Dubois, Per Stenström
SimWattch: Integrating Complete-System and User-Level Performance and Power Simulators. IEEE Micro 27 (4) (2007)
Md. Mafijul Islam, Alexander Busck, Mikael Engbom, Simji Lee, Michel Dubois, Per Stenström
Loop-level Speculative Parallelism in Embedded Applications. ICPP (2007)
Michel Dubois, Hyunyoung Lee, Lan Lin
STAMP: A Universal Algorithmic Model for Next-Generation Multithreaded Machines and Systems. IPDPS (2007)
Jaeheon Jeong, Michel Dubois
Cache Replacement Algorithms with Nonuniform Miss Costs. IEEE Trans. Computers 55 (4) (2006)
Jaeheon Jeong, Per Stenström, Michel Dubois
Simple penalty-sensitive replacement policies for caches. Conf. Computing Frontiers (2006)
Nasir Mohyuddin, Rashed Zafar Bhatti, Michel Dubois
Controlling leakage power with the replacement policy in slumberous caches. Conf. Computing Frontiers (2005)
Xiaogang Qiu, Michel Dubois
Moving Address Translation Closer to Memory in Distributed Shared-Memory Multiprocessors. IEEE Trans. Parallel Distributed Syst. 16 (7) (2005)
Michel Dubois
Fighting the memory wall with assisted execution. Conf. Computing Frontiers (2004)
Martin Kämpe, Per Stenström, Michel Dubois
Self-correcting LRU replacement policies. Conf. Computing Frontiers (2004)
Xiaogang Qiu, Michel Dubois
Tolerating Late Memory Traps in Dynamically Scheduled Processors. IEEE Trans. Computers 53 (6) (2004)
Adrian Moga, Michel Dubois
Scalability implications of software-implemented coherence. Comput. Syst. Sci. Eng. 18 (1) (2003)
Jaeheon Jeong, Michel Dubois
Cost-Sensitive Cache Replacement Algorithms. HPCA (2003)
Jianwei Chen, Michel Dubois, Per Stenström
Integrating complete-system and user-level performance/power simulators: the SimWattch approach. ISPASS (2003)
Michel Dubois, Jaeheon Jeong, Ashwini K. Nanda
Shared cache architectures for decision support systems. Perform. Evaluation 49 (1/4) (2002)
Martin Kämpe, Per Stenström, Michel Dubois
The FAB Predictor: Using Fourier Analysis to Predict the Outcome of Conditional Branches. HPCA (2002)
Xiaogang Qiu, Michel Dubois
Towards Virtually-Addressed Memory Hierarchies. HPCA (2001)
Fong Pong, Michel Dubois
Formal Automatic Verification of Cache Coherence in Multiprocessors with Relaxed Memory Models. IEEE Trans. Parallel Distributed Syst. 11 (9) (2000)
Jonas Skeppstedt, Michel Dubois
Compiler Controlled Prefetching for Multiprocessors Using Low-Overhead Traps and Prefetch Engines. J. Parallel Distributed Comput. 60 (5) (2000)
Jaeheon Jeong, Michel Dubois
Optimal Replacements in Caches with Two Miss Costs. SPAA (1999)
Xiaogang Qiu, Michel Dubois
Tolerating Late Memory Traps in ILP Processors. ISCA (1999)
Christopher Ho, Heidi E. Ziegler, Michel Dubois
In-Memory Directories: Eliminating the Cost of Directories in CC-NUMAs. SPAA (1998)
Fredrik Dahlgren, Michel Dubois, Per Stenström
Performance Evaluation and Cost Analysis of Cache Protocol Extensions for Shared-Memory Multiprocessors. IEEE Trans. Computers 47 (10) (1998)
Fong Pong, Michael C. Browne, Gunes Aybay, Andreas Nowatzyk, Michel Dubois
Design Verification of the S3.mp Cache-Coherent Shared-Memory System. IEEE Trans. Computers 47 (1) (1998)
Michel Dubois, Jaeheon Jeong, Yong Ho Song, Adrian Moga
Rapid Hardware Prototyping on RPM-2. IEEE Des. Test Comput. 15 (3) (1998)
Michel Dubois, Christoph Scheurich
Retrospective: Memory Access Buffering in Multiprocessors. 25 Years ISCA: Retrospectives and Reprints (1998)
Adrian Moga, Michel Dubois
The Effectiveness of SRAM Network Caches in Clustered DSMs. HPCA (1998)
Kangwoo Lee, Michel Dubois
Empirical Models of Miss Rates. Parallel Comput. 24 (2) (1998)
Fong Pong, Michel Dubois
Formal Verification of Complex Coherence Protocols Using Symbolic State Models. J. ACM 45 (4) (1998)
Xiaogang Qiu, Michel Dubois
Options for Dynamic Address Translation in COMAs. ISCA (1998)
Michel Dubois, Christoph Scheurich, Faye A. Briggs
Memory Access Buffering in Multiprocessors. 25 Years ISCA: Retrospectives and Reprints (1998)
Jonas Skeppstedt, Michel Dubois
Hybrid compiler/hardware prefetching for multiprocessors using low-overhead cache miss traps. ICPP (1997)
Fong Pong, Michel Dubois
Verification Techniques for Cache Coherence Protocols. ACM Comput. Surv. 29 (1) (1997)
Kangwoo Lee, Woo-Jong Han, Michel Dubois
Bottleneck-Free Interconnect and IO Subsystem in SPAX. ICPADS (1997)
Michel Cekleov, Michel Dubois
Virtual-address caches. Part 1: problems and solutions in uniprocessors. IEEE Micro 17 (5) (1997)
Adrian Moga, Michel Dubois, Alain Gefflaut
Hardware Versus Software Implementation of COMA. ICPP (1997)
Michel Cekleov, Michel Dubois
Virtual-address caches.2. Multiprocessor issues. IEEE Micro 17 (6) (1997)
Per Stenström, Mats Brorsson, Fredrik Dahlgren, Håkan Grahn, Michel Dubois
Boosting the Performance of Shared Memory Multiprocessors. Computer 30 (7) (1997)
Fong Pong, Michel Dubois
Formal Verification of Delayed Consistency Protocols. IPPS (1996)
Adrian Moga, Michel Dubois
Performance of Asynchronous Linear Iterations with Random Delays. IPPS (1996)
Aydin Üresin, Michel Dubois
Effects of Asynchronism on the Convergence Rate of Iterative Algorithms. J. Parallel Distributed Comput. 34 (1) (1996)
Fong Pong, Michel Dubois
A New Approach for the Verification of Cache Coherence Protocols. IEEE Trans. Parallel Distributed Syst. 6 (8) (1995)
Fredrik Dahlgren, Michel Dubois, Per Stenström
Sequential Hardware Prefetching in Shared-Memory Multiprocessors. IEEE Trans. Parallel Distributed Syst. 6 (7) (1995)
Fong Pong, Andreas Nowatzyk, Gunes Aybay, Michel Dubois
Verifying Distributed Directory-Based Cahce Coherence Protocols: S3.mp, a Case Study. Euro-Par (1995)
Luiz André Barroso, Michel Dubois
Performance Evaluation of the Slotted Ring Multiprocessor. IEEE Trans. Computers 44 (7) (1995)
Luiz André Barroso, Sasan Iman, Jaeheon Jeong, Koray Öner, Michel Dubois
RPM: A Rapid Prototyping Engine for Multiprocessor Systems. Computer 28 (2) (1995)
Håkan Grahn, Per Stenström, Michel Dubois
Implementation and evaluation of update-based cache protocols under relaxed memory consistency models. Future Gener. Comput. Syst. 11 (3) (1995)
Michel Dubois, Jonas Skeppstedt, Per Stenström
Essential Misses and Data Traffic in Coherence Protocols. J. Parallel Distributed Comput. 29 (2) (1995)
Koray Öner, Luiz André Barroso, Sasan Iman, Jaeheon Jeong, Krishnan Ramamurthy, Michel Dubois
The Design of RPM: An FPGA-based Multiprocessor Emulator. FPGA (1995)
Fong Pong, Per Stenström, Michel Dubois
An Integrated Methodology for the Verification of Directory-Based Cache Protocols. ICPP (1) (1994)
Fredrik Dahlgren, Michel Dubois, Per Stenström
Combined Performance Gains of Simple Cache Protocol Extensions. ISCA (1994)
Jacqueline Chame, Michel Dubois
Cache Inclusion and Processor Sampling in Multiprocessor Simulations. SIGMETRICS (1993)
Michel Dubois, Jonas Skeppstedt, Livio Ricciulli, Krishnan Ramamurthy, Per Stenström
The Detection and Elimination of Useless Misses in Multiprocessors. ISCA (1993)
Fredrik Dahlgren, Michel Dubois, Per Stenström
Fixed and Adaptive Sequential Prefetching in Shared Memory Multiprocessors. ICPP (1) (1993)
Luiz André Barroso, Michel Dubois
The Performance of Cache-Coherent Ring-based Multiprocessors. ISCA (1993)
Koray Öner, Michel Dubois
Effects of Memory Latencies on Non-Blocking Processor/Cache Architectures. International Conference on Supercomputing (1993)
Fong Pong, Michel Dubois
The Verification of Cache Coherence Protocols. SPAA (1993)
Yung-Syau Chen, Michel Dubois
Cache Protocols with Partial Block Invalidations. IPPS (1993)
Fong Pong, Michel Dubois
Correctness of a Directory-Based Cache Coherence Protocol: Early Experience. SPDP (1993)
Michel Dubois, Luiz André Barroso, Yung-Syau Chen, Koray Öner
Scalability Problems in Multiprocessors with Private Caches. PARLE (1992)
Michel Dubois
Special Issue on Memory System Architectures for Scalable Multiprocessors. J. Parallel Distributed Comput. 15 (4) (1992)
Ashfaq A. Khokhar, Michel Dubois
Matching Algorithms and Architecture in Hierarchical Shared-Memory Multiprocessor (HMS) Systems. IPPS (1992)
Luiz André Barroso, Michel Dubois
Cache Coherence on a Slotted Ring. ICPP (1) (1991)
Michel Dubois, Jin-Chin Wang, Luiz André Barroso, Kangwoo Lee, Yung-Syau Chen
Delayed consistency and its effects on the miss rate of parallel programs. SC (1991)
Jin-Chin Wang, Michel Dubois, Faye A. Briggs
Analytical Modeling for Finite Cache Effects. ICPP (1) (1991)
Christoph Scheurich, Michel Dubois
Lockup-free Caches in High-Performance Multiprocessors. J. Parallel Distributed Comput. 11 (1) (1991)
Michel Dubois, Jin-Chin Wang
Shared Block Contention in a Cache Coherence Protocol. IEEE Trans. Computers 40 (5) (1991)
Michel Dubois, Faye A. Briggs
The Run-Time Efficiency of Parallel Asynchronous Algorithms. IEEE Trans. Computers 40 (11) (1991)
Aydin Üresin, Michel Dubois
Asynchronous Iterations with Bounded Delay. ICPP (3) (1990)
Sharad Mehrotra, Chien-Ming Cheng, Kai Hwang, Michel Dubois, Dhabaleswar K. Panda
Algorithm-Driven Simulation and Performance Projection of a RISC-based Orthogonal Multiprocessor. ICPP (3) (1990)
Anastasios A. Economides, Michel Dubois
Transient Models of Bus-Based Multiprocessors. ICPP (1) (1990)
Jin-Chin Wang, Michel Dubois
Performance comparison of cache coherence protocols based on the access burst model. Comput. Syst. Sci. Eng. 5 (3) (1990)
Kai Hwang, Michel Dubois, Dhabaleswar K. Panda, S. Rao, Shisheng Shang, Aydin Üresin, W. Mao, H. Nair, M. Lytwyn, F. Hsieh, J. Liu, Sharad Mehrotra, Chien-Ming Cheng
OMP: a RISC-based multiprocessor using orthogonal-access memories and multiple spanning buses. ICS (1990)
Michel Dubois, Christoph Scheurich
Memory Access Dependencies in Shared-Memory Multiprocessors. IEEE Trans. Software Eng. 16 (6) (1990)
Aydin Üresin, Michel Dubois
Parallel Asynchronous Algorithms for Discrete Data J. ACM 37 (3) (1990)
Shreekant S. Thakkar, Michel Dubois, Anthony T. Laundrie, Gurindar S. Sohi, David V. James, Stein Gjessing, Manu Thapar, Bruce Delagi, Michael J. Carlton, Alvin M. Despain
Scalable Shared-Memory Multiprocessor Architectures. Computer 23 (6) (1990)
Michel Dubois, Shreekant S. Thakkar
Cache Architectures in Tightly Coupled Multiprocessors - Guest Editors' Introduction to the Special Issue. Computer 23 (6) (1990)
Christoph Scheurich, Michel Dubois
Dynamic Page Migration in Multiprocessors with Distributed Global Memory. IEEE Trans. Computers 38 (8) (1989)
Aydin Üresin, Michel Dubois
Sufficient conditions for the convergence of asynchronous iterations. Parallel Comput. 10 (1) (1989)

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Publication Activity (10 Years)

Top Topics

Top Venues

Michel Dubois