Alvin M. Despain

Publication Activity (10 Years)

Years Active: 1974-2006
Publications (10 Years): 0

Publications

Won Woo Ro, Stephen P. Crago, Alvin M. Despain, Jean-Luc Gaudiot
Design and evaluation of a hierarchical decoupled architecture. J. Supercomput. 38 (3) (2006)
Won Woo Ro, Jean-Luc Gaudiot, Stephen P. Crago, Alvin M. Despain
HiDISC: A Decoupled Architecture for Data-Intensive Application. IPDPS (2003)
Petros A. Ioannou, Elias B. Kosmatopoulos, Alvin M. Despain
Position error signal estimation at high sampling rates using data and servo sector measurements. IEEE Trans. Control. Syst. Technol. 11 (3) (2003)
Petros A. loannou, Elias B. Kosmatopoulos, Alvin M. Despain
Position error signal estimation at high sampling rates using data and servo sector measurements. CDC (2002)
Chi-Ying Tsui, Massoud Pedram, Alvin M. Despain
Low-power state assignment targeting two- and multilevel logic implementations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17 (12) (1998)
Kevin M. Obenland, Alvin M. Despain
Simulating the Effect of Decoherence and Inaccuracies on a Quantum Computer. QCQC (1998)
Vason P. Srini, Tam M. Nguyen, Darren R. Busing, Michael J. Carlton, Bruce K. Holmer, Georges E. Smine, Alvin M. Despain
Design and Simulation of the Aquarius-II Multiprocessor. J. Syst. Integr. 7 (2) (1997)
Shihming Liu, Massoud Pedram, Alvin M. Despain
State assignment based on two-dimensional placement and hypercube mapping. Integr. 24 (2) (1997)
Chi-Ying Tsui, José Monteiro, Massoud Pedram, Srinivas Devadas, Alvin M. Despain, Bill Lin
Correction to "Power Estimation Methods for Sequential Logic Circuits" [Correspondence]. IEEE Trans. Very Large Scale Integr. Syst. 4 (4) (1996)
Bruce K. Holmer, Barton Sano, Michael J. Carlton, Peter Van Roy, Alvin M. Despain
Design and Analysis of Hardware for High-Performance Prolog. J. Log. Program. 29 (1-3) (1996)
Chi-Ying Tsui, José Monteiro, Massoud Pedram, Srinivas Devadas, Alvin M. Despain, Bill Lin
Power estimation methods for sequential logic circuits. IEEE Trans. Very Large Scale Integr. Syst. 3 (3) (1995)
Ching-Long Su, Alvin M. Despain
Cache design trade-offs for power and performance optimization: a case study. ISLPD (1995)
Ching-Long Su, Alvin M. Despain
Cache designs for energy efficiency. HICSS (1) (1995)
Ing-Jer Huang, Alvin M. Despain
Synthesis of application specific instruction sets. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14 (6) (1995)
Shihming Liu, Massoud Pedram, Alvin M. Despain
A Fast State Assignment Procedure for Large FSMs. DAC (1995)
Shihming Liu, Massoud Pedram, Alvin M. Despain
PLATO P: PLA Timing Optimization by Partitioning. ISCAS (1995)
Apoorv Srivastava, Yong-Seon Koh, Barton Sano, Alvin M. Despain
190-MHz CMOS 4-Kbyte Pipelined Caches. ISCAS (1995)
Ching-Long Su, Alvin M. Despain
Hardware-software co-designing benchmark-driven superpipelined instruction set processors. COMPSAC (1994)
Chi-Ying Tsui, Massoud Pedram, Chih-Ang Chen, Alvin M. Despain
Low power state assignment targeting two-and multi-level logic implementations. ICCAD (1994)
Ching-Long Su, Chin-Chi Teng, Alvin M. Despain
A Study of Cache Hashing Functions for Symbolic Applications in Micro-Parallel Processors. ICPADS (1994)
Ing-Jer Huang, Alvin M. Despain
Generating instruction sets and microarchitectures from applications. ICCAD (1994)
Ching-Long Su, Alvin M. Despain
Branch with Masked Squashing in Superpipelined Processors. ISCA (1994)
Ching-Long Su, Chi-Ying Tsui, Alvin M. Despain
Lower Power Architecture Design and Compilation Techniques for High-Performance Processors. COMPCON (1994)
Ching-Long Su, Chi-Ying Tsui, Alvin M. Despain
Saving Power in the Control Path of Embedded Processors. IEEE Des. Test Comput. 11 (4) (1994)
Ching-Long Su, Alvin M. Despain
Minimizing branch misprediction penalties for superpipelined processors. MICRO (1994)
Ing-Jer Huang, Alvin M. Despain
Synthesis of Instruction Sets for Pipelined Microprocessors. DAC (1994)
Chi-Ying Tsui, Massoud Pedram, Alvin M. Despain
Power efficient technology decomposition and mapping under an extended power consumption model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13 (9) (1994)
Chi-Ying Tsui, Massoud Pedram, Alvin M. Despain
Exact and Approximate Methods for Calculating Signal and Transition Probabilities in FSMs. DAC (1994)
Chi-Ying Tsui, Massoud Pedram, Alvin M. Despain
Efficient estimation of dynamic power consumption under a real delay model. ICCAD (1993)
Iksoo Pyo, Alvin M. Despain
PDAS: Processor design automation system. EURO-DAC (1993)
Ing-Jer Huang, Alvin M. Despain
Hardware/software resolution of pipeline hazards in pipeline synthesis of instruction set processors. ICCAD (1993)
Ing-Jer Huang, Alvin M. Despain
An extended classification of inter-instruction dependency and its application in automatic synthesis of pipelined processors. MICRO (1993)
Barton Sano, Alvin M. Despain
The 16-fold way: a microparallel taxonomy. MICRO (1993)
Chi-Ying Tsui, Massoud Pedram, Alvin M. Despain
Technology Decomposition and Mapping Targeting Low Power Dissipation. DAC (1993)
Apoorv Srivastava, Alvin M. Despain
Prophetic branches: a branch architecture for code compaction and efficient execution. MICRO (1993)
Iksoo Pyo, Ching-Long Su, Ing-Jer Huang, Kuo-Rueih Pan, Yong-Seon Koh, Chi-Ying Tsui, Hsu-Tsun Chen, Gino Cheng, Shihming Liu, Shiqun Wu, Alvin M. Despain
Application-Driven Design Automation for Microprocessor Design. DAC (1992)
Ing-Jer Huang, Alvin M. Despain
High Level Synthesis of Pipelined Instruction Set Processors and Back-End Compilers. DAC (1992)
Peter Van Roy, Alvin M. Despain
High-Performance Logic Programming with the Aquarius Prolog Compiler. Computer 25 (1) (1992)
Saul Amarel, Alvin M. Despain, H. Penny Nii, Louis I. Steinberg, Marty Tenenbaum, Peter M. Will
AI and Design. IJCAI (1991)
Alvin M. Despain, Robert Yung
An integrated prolog architecture for symbolic and numeric executions. Ann. Math. Artif. Intell. 4 (1991)
Bruce K. Holmer, Alvin M. Despain
Viewing Instruction Set Design as an Optimization Problem. MICRO (1991)
Barry S. Fagin, Alvin M. Despain
The Performance of Parallel Prolog Programs. IEEE Trans. Computers 39 (12) (1990)
Peter Van Roy, Alvin M. Despain
The Benefits of Global Dataflow Analysis for an Optimizing Prolog Compiler. NACLP (1990)
Bruce K. Holmer, Barton Sano, Michael J. Carlton, Peter Van Roy, Ralph Clarke Haygood, William R. Bush, Alvin M. Despain, Joan M. Pendleton, Tep P. Dobry
Fast Prolog with an Extended General Purpose Architecture. ISCA (1990)
Darren R. Busing, Vason P. Srini, Georges E. Smine, Michael J. Carlton, Alvin M. Despain
The Aquarius IIU System. ICSI (1990)
Shreekant S. Thakkar, Michel Dubois, Anthony T. Laundrie, Gurindar S. Sohi, David V. James, Stein Gjessing, Manu Thapar, Bruce Delagi, Michael J. Carlton, Alvin M. Despain
Scalable Shared-Memory Multiprocessor Architectures. Computer 23 (6) (1990)
Alvin M. Despain
Prolog at Berkeley. COMPCON (1988)
Tam M. Nguyen, Vason P. Srini, Alvin M. Despain
A two-tier memory architecture for high-performance multiprocessor systems. ICS (1988)
Alvin M. Despain, Yale N. Patt, Vason P. Srini, Philip Bitar, William R. Bush, C. Chien, Wayne Citrin, Barry Fagin, Wenwei Hwu, Stephen W. Melvin, Rick McGeer, Ashok Singhal, Michael Shebanow, Peter Van Roy
Aquarius. SIGARCH Comput. Archit. News 15 (1) (1987)
Hervé J. Touati, Alvin M. Despain
An Empirical Study of the Warren Abstract Machine. SLP (1987)
William R. Bush, Gino Cheng, Patrick C. McGeer, Alvin M. Despain
Experience with Prolog as a Hardware Specification Language. SLP (1987)
Barry S. Fagin, Alvin M. Despain
Performance Studies of a Parallel Prolog Architecture. ISCA (1987)
Alvin M. Despain, Yale N. Patt, Tep P. Dobry, Jung-Herng Chang, Wayne Citrin
High Performance Prolog, The Multiplicative Effect of Several Levels of Implementation. COMPCON (1986)
Philip Bitar, Alvin M. Despain
Multiprocessor Cache Synchronization: Issues, Innovations, Evolution. ISCA (1986)
Jonathan D. Pincus, Alvin M. Despain
Delay reduction using simulated annealing. DAC (1986)
Alvin M. Despain, Allen M. Peterson, Oscar S. Rothaus, Erling Wold
Fast fourier transform processors using Gaussian residue arithmetic. J. Parallel Distributed Comput. 2 (3) (1985)
Barry S. Fagin, Yale N. Patt, Vason P. Srini, Alvin M. Despain
Compiling Prolog into microcode: a case study using the NCR/32-000. MICRO (1985)
Tep P. Dobry, Alvin M. Despain, Yale N. Patt
Performance Studies of a Prolog Machine Architecture. ISCA (1985)
Jung-Herng Chang, Alvin M. Despain, Doug DeGroot
AND-Parallelism of Logic Programs Based on a Static Data Dependency Analysis. COMPCON (1985)
Jung-Herng Chang, Alvin M. Despain
Semi-Intelligent Backtracking of Prolog Based on Static Data Dependency Analysis. SLP (1985)
Alvin M. Despain, Yale N. Patt
Aquarius - A High Performance Computing System for Symbolic/Numeric Applications. COMPCON (1985)
Tep P. Dobry, Yale N. Patt, Alvin M. Despain
Design decisions influencing the microarchitecture for a Prolog machine. MICRO (1984)
Erling Wold, Alvin M. Despain
Pipeline and Parallel-Pipeline FFT Processors for VLSI Implementations. IEEE Trans. Computers 33 (5) (1984)
Alvin M. Despain, Yale N. Patt
The Aquarius Project. COMPCON (1984)
Alvin M. Despain
Very Fast Fourier Transform Algorithms Hardware for Implementation. IEEE Trans. Computers 28 (5) (1979)
Alvin M. Despain, David A. Patterson
X-Tree: A Tree Structured Multi-Processor Computer Architecture. ISCA (1978)
Carlo H. Séquin, Alvin M. Despain, David A. Patterson
Communication In X-TREE, A Modular Multiprocessor System. ACM Annual Conference (1) (1978)
Alvin M. Despain
Fourier Transform Computers Using CORDIC Iterations. IEEE Trans. Computers 23 (10) (1974)