Yale N. Patt

ORCID

Publication Activity (10 Years)

Years Active: 1967-2024
Publications (10 Years): 16

Top Venues

Publications

Yale N. Patt
Hetero: Where we've been, Where we are, and What Next? IPDPS (Workshops) (2024)
Yale N. Patt
HCW 2024 Keynote: Hetero: Where we've been, Where we are, and What Next? IPDPS (Workshops) (2024)
Aniket Anand Deshmukh, Lingzhe Chester Cai, Yale N. Patt
Alternate Path Fetch. ISCA (2024)
Yale N. Patt
The CORRECT First Course in Computing for Serious Students. Computer 57 (4) (2024)
Ali Fakhrzadehgan, Yale N. Patt, Prashant J. Nair, Moinuddin K. Qureshi
SafeGuard: Reducing the Security Risk from Row-Hammer via Low-Cost Integrity Protection. HPCA (2022)
Aniket Deshmukh, Yale N. Patt
Criticality Driven Fetch. MICRO (2021)
Stephen Pruett, Yale N. Patt
Branch Runahead: An Alternative to Branch Prediction for Impossible to Predict Branches. MICRO (2021)
Faruk Guvenilir, Yale N. Patt
Tailored Page Sizes. ISCA (2020)
Siavash Zangeneh, Stephen Pruett, Sangkug Lym, Yale N. Patt
BranchNet: A Convolutional Neural Network to Predict Hard-To-Predict Branches. MICRO (2020)
Stephen Pruett, Yale N. Patt
Dynamic Merge Point Prediction. CoRR (2020)
Ben Lin, Michael B. Healy, Rustam Miftakhutdinov, Philip G. Emma, Yale N. Patt
Duplicon Cache: Mitigating Off-Chip Memory Bank and Bank Group Conflicts Via Data Duplication. MICRO (2018)
Milad Hashemi, Debbie Marr, Doug Carmean, Yale N. Patt
Efficient Execution of Bursty Applications. IEEE Comput. Archit. Lett. 15 (2) (2016)
Milad Hashemi, Onur Mutlu, Yale N. Patt
Continuous runahead: Transparent hardware acceleration for memory intensive workloads. MICRO (2016)
Onur Mutlu, Rich Belgard, Thomas R. Gross, Norman P. Jouppi, John L. Hennessy, Steven A. Przybylski, Chris Rowen, Yale N. Patt, Wen-mei W. Hwu, Stephen W. Melvin, Michael Shebanow, Tse-Yu Yeh, Andy Wolfe
Common Bonds: MIPS, HPS, Two-Level Branch Prediction, and Compressed Code RISC Processor. IEEE Micro 36 (4) (2016)
Milad Hashemi, Khubaib, Eiman Ebrahimi, Onur Mutlu, Yale N. Patt
Accelerating Dependent Cache Misses with an Enhanced Memory Controller. ISCA (2016)
Yale N. Patt
Greater Performance and Better Efficiency: Predicated Execution has shown us the way. PACT (2016)
Milad Hashemi, Yale N. Patt
Filtered runahead execution with a runahead buffer. MICRO (2015)
Tse-Yu Yeh, Deborah T. Marr, Yale N. Patt
Author retrospective for increasing the instruction fetch rate via multiple branch prediction and a branch address cache. ICS 25th Anniversary (2014)
José A. Joao, M. Aater Suleman, Onur Mutlu, Yale N. Patt
Utility-based acceleration of multithreaded applications on asymmetric CMPs. ISCA (2013)
Sani R. Nassif, Yale N. Patt, Magdy S. Abadir
Keynote 1 - VLSI 2.0: R&D Post Moore. VLSI-SoC (2013)
Rustam Miftakhutdinov, Eiman Ebrahimi, Yale N. Patt
Predicting Performance Impact of DVFS for Realistic Memory Systems. MICRO (2012)
Yale N. Patt
High performance supercomputers: should the individual processor be more than a brick? ICS (2012)
José A. Joao, M. Aater Suleman, Onur Mutlu, Yale N. Patt
Bottleneck identification and scheduling in multithreaded applications. ASPLOS (2012)
Marco A. Z. Alves, Khubaib, Eiman Ebrahimi, Veynu Narasiman, Carlos Villavieja, Philippe Olivier Alexandre Navaux, Yale N. Patt
Energy Savings via Dead Sub-Block Prediction. SBAC-PAD (2012)
Eiman Ebrahimi, Chang Joo Lee, Onur Mutlu, Yale N. Patt
Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multicore Memory Systems. ACM Trans. Comput. Syst. 30 (2) (2012)
Khubaib, M. Aater Suleman, Milad Hashemi, Chris Wilkerson, Yale N. Patt
MorphCore: An Energy-Efficient Microarchitecture for High Performance ILP and High Throughput TLP. MICRO (2012)
Eiman Ebrahimi, Chang Joo Lee, Onur Mutlu, Yale N. Patt
Prefetch-aware shared resource management for multi-core systems. ISCA (2011)
Yale N. Patt, Onur Mutlu
Top Picks [Guest editors' introduction]. IEEE Micro 31 (1) (2011)
Eiman Ebrahimi, Rustam Miftakhutdinov, Chris Fallin, Chang Joo Lee, José A. Joao, Onur Mutlu, Yale N. Patt
Parallel application memory scheduling. MICRO (2011)
M. Aater Suleman, Onur Mutlu, José A. Joao, Khubaib, Yale N. Patt
Data Marshaling for Multicore Systems. IEEE Micro 31 (1) (2011)
Veynu Narasiman, Michael Shebanow, Chang Joo Lee, Rustam Miftakhutdinov, Onur Mutlu, Yale N. Patt
Improving GPU performance via large warps and two-level warp scheduling. MICRO (2011)
Chang Joo Lee, Onur Mutlu, Veynu Narasiman, Yale N. Patt
Prefetch-Aware Memory Controllers. IEEE Trans. Computers 60 (10) (2011)
M. Aater Suleman, Moinuddin K. Qureshi, Khubaib, Yale N. Patt
Feedback-directed pipeline parallelism. PACT (2010)
M. Aater Suleman, Onur Mutlu, Moinuddin K. Qureshi, Yale N. Patt
Accelerating Critical Section Execution with Asymmetric Multicore Architectures. IEEE Micro 30 (1) (2010)
M. Aater Suleman, Onur Mutlu, José A. Joao, Khubaib, Yale N. Patt
Data marshaling for multi-core architectures. ISCA (2010)
Eiman Ebrahimi, Chang Joo Lee, Onur Mutlu, Yale N. Patt
Fairness via source throttling: a configurable and high-performance fairness substrate for multi-core memory systems. ASPLOS (2010)
José A. Joao, Onur Mutlu, Yale N. Patt
Flexible reference-counting-based hardware acceleration for garbage collection. ISCA (2009)
Eiman Ebrahimi, Onur Mutlu, Chang Joo Lee, Yale N. Patt
Coordinated control of multiple prefetchers in multi-core systems. MICRO (2009)
Chang Joo Lee, Veynu Narasiman, Onur Mutlu, Yale N. Patt
Improving memory bank-level parallelism in the presence of prefetching. MICRO (2009)
Hyesoon Kim, José A. Joao, Onur Mutlu, Chang Joo Lee, Yale N. Patt, Robert Cohn
Virtual Program Counter (VPC) Prediction: Very Low Cost Indirect Branch Prediction Using Conditional Branch Prediction Hardware. IEEE Trans. Computers 58 (9) (2009)
Yale N. Patt
Multi-core demands multi-interfaces. PPOPP (2009)
Yale N. Patt
Multi-core demands multi-interfaces. HPCA (2009)
Yale N. Patt
The Challenges of Multicore: Information and Mis-Information. ARCS (2009)
M. Aater Suleman, Onur Mutlu, Moinuddin K. Qureshi, Yale N. Patt
Accelerating critical section execution with asymmetric multi-core architectures. ASPLOS (2009)
Eiman Ebrahimi, Onur Mutlu, Yale N. Patt
Techniques for bandwidth-efficient prefetching of linked data structures in hybrid prefetching systems. HPCA (2009)
Yale N. Patt
What Else Is Broken? Can We Fix It? SAMOS (2009)
M. Aater Suleman, Moinuddin K. Qureshi, Yale N. Patt
Feedback-driven threading: power-efficient and high-performance execution of multi-threaded workloads on CMPs. ASPLOS (2008)
José A. Joao, Onur Mutlu, Hyesoon Kim, Rishi Agarwal, Yale N. Patt
Improving the performance of object-oriented languages with dynamic predication of indirect jumps. ASPLOS (2008)
Moinuddin K. Qureshi, Aamer Jaleel, Yale N. Patt, Simon C. Steely Jr., Joel S. Emer
Set-Dueling-Controlled Adaptive Insertion for High-Performance Caching. IEEE Micro 28 (1) (2008)
Francis Tseng, Yale N. Patt
Achieving Out-of-Order Performance with Almost In-Order Complexity. ISCA (2008)
Chang Joo Lee, Onur Mutlu, Veynu Narasiman, Yale N. Patt
Prefetch-Aware DRAM Controllers. MICRO (2008)
José A. Joao, Onur Mutlu, Hyesoon Kim, Yale N. Patt
Dynamic Predication of Indirect Jumps. IEEE Comput. Archit. Lett. 7 (1) (2008)
Chang Joo Lee, Hyesoon Kim, Onur Mutlu, Yale N. Patt
Performance-aware speculation control using wrong path usefulness prediction. HPCA (2008)
Yale N. Patt
Can They Be Fixed: Some Thoughts After 40 Years in the Business. SAMOS (2008)
Hyesoon Kim, José A. Joao, Onur Mutlu, Yale N. Patt
Diverge-Merge Processor: Generalized and Energy-Efficient Dynamic Predication. IEEE Micro 27 (1) (2007)
Moinuddin K. Qureshi, Aamer Jaleel, Yale N. Patt, Simon C. Steely Jr., Joel S. Emer
Adaptive insertion policies for high performance caching. ISCA (2007)
José A. Joao, Onur Mutlu, Hyesoon Kim, Yale N. Patt
Dynamic Predication of Indirect Jumps. IEEE Comput. Archit. Lett. 6 (2) (2007)
Santhosh Srinath, Onur Mutlu, Hyesoon Kim, Yale N. Patt
Feedback Directed Prefetching: Improving the Performance and Bandwidth-Efficiency of Hardware Prefetchers. HPCA (2007)
Joel S. Emer, Mark D. Hill, Yale N. Patt, Joshua J. Yi, Derek Chiou, Resit Sendag
Single-Threaded vs. Multithreaded: Where Should We Focus? IEEE Micro 27 (6) (2007)
Hyesoon Kim, José A. Joao, Onur Mutlu, Yale N. Patt
Profile-assisted Compiler Support for Dynamic Predication in Diverge-Merge Processors. CGO (2007)
Moinuddin K. Qureshi, M. Aater Suleman, Yale N. Patt
Line Distillation: Increasing Cache Capacity by Filtering Unused Words in Cache Lines. HPCA (2007)
Hyesoon Kim, José A. Joao, Onur Mutlu, Chang Joo Lee, Yale N. Patt, Robert Cohn
VPC prediction: reducing the cost of indirect branches via hardware-based dynamic devirtualization. ISCA (2007)
Yale N. Patt
The Transformation Hierarchy in the Era of Multi-core. HiPC (2007)
Hyesoon Kim, José A. Joao, Onur Mutlu, Yale N. Patt
Diverge-Merge Processor (DMP): Dynamic Predicated Execution of Complex Control-Flow Graphs Based on Frequently Executed Paths. MICRO (2006)
Moinuddin K. Qureshi, Yale N. Patt
Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches. MICRO (2006)
Yale N. Patt
Computer Architecture Research and Future Microprocessors: Where Do We Go from Here? ISCA (2006)
Jean-Luc Gaudiot, Yale N. Patt, Kevin Skadron
Foreword. IEEE Comput. Archit. Lett. 5 (2) (2006)
Onur Mutlu, Hyesoon Kim, Yale N. Patt
Address-Value Delta (AVD) Prediction: A Hardware Technique for Efficiently Parallelizing Dependent Cache Misses. IEEE Trans. Computers 55 (12) (2006)
Onur Mutlu, Hyesoon Kim, Yale N. Patt
Efficient Runahead Execution: Power-Efficient Memory Latency Tolerance. IEEE Micro 26 (1) (2006)
Hyesoon Kim, Onur Mutlu, Yale N. Patt, Jared Stark
Wish Branches: Enabling Adaptive and Aggressive Predicated Execution. IEEE Micro 26 (1) (2006)
Hyesoon Kim, M. Aater Suleman, Onur Mutlu, Yale N. Patt
2D-Profiling: Detecting Input-Dependent Branches with a Single Input Data Set. CGO (2006)
Moinuddin K. Qureshi, Daniel N. Lynch, Onur Mutlu, Yale N. Patt
A Case for MLP-Aware Cache Replacement. ISCA (2006)
Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt
An Analysis of the Performance Impact of Wrong-Path Memory References on Out-of-Order and Runahead Execution Processors. IEEE Trans. Computers 54 (12) (2005)
Onur Mutlu, Hyesoon Kim, Jared Stark, Yale N. Patt
On Reusing the Results of Pre-Executed Instructions in a Runahead Execution Processor. IEEE Comput. Archit. Lett. 4 (1) (2005)
Onur Mutlu, Hyesoon Kim, Yale N. Patt
Techniques for Efficient Processing in Runahead Execution Engines. ISCA (2005)
Yale N. Patt
The microprocessor of the year 2014: do Pentium 4, Pentium M, and Power 5 provide any hints? AICCSA (2005)
Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt
Using the First-Level Caches as Filters to Reduce the Pollution Caused by Speculative Memory References. Int. J. Parallel Program. 33 (5) (2005)
Onur Mutlu, Hyesoon Kim, Yale N. Patt
Address-Value Delta (AVD) Prediction: Increasing the Effectiveness of Runahead Execution by Exploiting Regular Memory Allocation Patterns. MICRO (2005)
Moinuddin K. Qureshi, David Thompson, Yale N. Patt
The V-Way Cache: Demand Based Associativity via Global Replacement. ISCA (2005)
Yale N. Patt
A Unifying Theory of Distributed Processing (Or, The Chutzpah One Should Expect When You Invite a Microarchitect into Your Sandbox). IPDPS (2005)
Moinuddin K. Qureshi, Onur Mutlu, Yale N. Patt
Microarchitecture-Based Introspection: A Technique for Transient-Fault Tolerance in Microprocessors. DSN (2005)
Hyesoon Kim, Onur Mutlu, Jared Stark, Yale N. Patt
Wish Branches: Combining Conditional Branching and Predication for Adaptive Predicated Execution. MICRO (2005)
Yale N. Patt
Opening and keynote 1. ISPASS (2004)
Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt
Cache Filtering Techniques to Reduce the Negative Impact of Useless Speculative Memory References on Processor Performance. SBAC-PAD (2004)
Brad Calder, Daniel Citron, Yale N. Patt, James E. Smith
The future of simulation: A field of dreams. ISPASS (2004)
David N. Armstrong, Hyesoon Kim, Onur Mutlu, Yale N. Patt
Wrong Path Events: Exploiting Unusual and Illegal Program Behavior for Early Misprediction Detection and Recovery. MICRO (2004)
Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt
Understanding the effects of wrong-path memory references on processor performance. WMPI (2004)
Onur Mutlu, Jared Stark, Chris Wilkerson, Yale N. Patt
Runahead Execution: An Effective Alternative to Large Instruction Windows. IEEE Micro 23 (6) (2003)
Onur Mutlu, Jared Stark, Chris Wilkerson, Yale N. Patt
Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-Order Processors. HPCA (2003)
Yale N. Patt
The High Performance Microprocessor in the Year 2013: What Will It Look Like? What It Won't Look Like? HiPC (2003)
Paul Racunas, Yale N. Patt
Partitioned first-level cache design for clustered microarchitectures. ICS (2003)
Yale N. Patt
Teaching and teaching computer architecture: two very different topics: (some opinions about each). WCAE (2003)
Robert S. Chappell, Francis Tseng, Adi Yoaz, Yale N. Patt
Microarchitectural support for precomputation microthreads. MICRO (2002)
Stephen W. Melvin, Yale N. Patt
Handling of packet dependencies: a critical issue for highly parallel network processors. CASES (2002)
Robert S. Chappell, Francis Tseng, Yale N. Patt, Adi Yoaz
Difficult-Path Branch Prediction Using Subordinate Microthreads. ISCA (2002)
Mary D. Brown, Yale N. Patt
Using Internal Redundant Representations and Limited Bypass to Support Pipelined Adders and Register Files. HPCA (2002)
Mary D. Brown, Jared Stark, Yale N. Patt
Select-free instruction scheduling logic. MICRO (2001)
Judith L. Gersting, Peter B. Henderson, Philip Machanick, Yale N. Patt
Programming early considered harmful. SIGCSE (2001)
Yale N. Patt
Requirements, bottlenecks, and good fortune: agents for microprocessor evolution. Proc. IEEE 89 (11) (2001)
Yale N. Patt
Higher and Higher Performance Microprocessors: Are The Problems Just Too Hard To Solve? EUROMICRO (2000)

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Publication Activity (10 Years)

Top Topics

Top Venues

Yale N. Patt