Michael Shebanow

Publication Activity (10 Years)

Years Active: 1985-2016
Publications (10 Years): 1

Top Topics

Industry Standard

Prediction Algorithm

Top Venues

Publications

Onur Mutlu, Rich Belgard, Thomas R. Gross, Norman P. Jouppi, John L. Hennessy, Steven A. Przybylski, Chris Rowen, Yale N. Patt, Wen-mei W. Hwu, Stephen W. Melvin, Michael Shebanow, Tse-Yu Yeh, Andy Wolfe
Common Bonds: MIPS, HPS, Two-Level Branch Prediction, and Compressed Code RISC Processor. IEEE Micro 36 (4) (2016)
Michael Shebanow
Peta Thread Computing [Keynote I]. ISPASS (2013)
Veynu Narasiman, Michael Shebanow, Chang Joo Lee, Rustam Miftakhutdinov, Onur Mutlu, Yale N. Patt
Improving GPU performance via large warps and two-level warp scheduling. MICRO (2011)
Michael Shebanow
Pervasive massively multithreaded GPU processors. Conf. Computing Frontiers (2009)
Mike Simone, A. Essen, A. Ike, A. Krishnamoorthy, Tak Maruyama, Niteen Patkar, M. Ramaswami, Michael Shebanow, V. Thirumalaiswamy, DeForest Tovey
Implementation Trade-Offs in Using a Restricted Data Flow Architecture in a High Performance RISC Microprocessor. ISCA (1995)
Michael Butler, Tse-Yu Yeh, Yale N. Patt, Mitch Alsup, Hunter Scales, Michael Shebanow
Single Instruction Stream Parallelism is Greater Than Two. ISCA (1991)
Stephen W. Melvin, Michael Shebanow, Yale N. Patt
Hardware support for large atomic units in dynamically scheduled machines. MICRO (1988)
Alvin M. Despain, Yale N. Patt, Vason P. Srini, Philip Bitar, William R. Bush, C. Chien, Wayne Citrin, Barry Fagin, Wenwei Hwu, Stephen W. Melvin, Rick McGeer, Ashok Singhal, Michael Shebanow, Peter Van Roy
Aquarius. SIGARCH Comput. Archit. News 15 (1) (1987)
James E. Wilson, Stephen W. Melvin, Michael Shebanow, Wen-mei W. Hwu, Yale N. Patt
On tuning the microarchitecture of an HPS implementation of the VAX. MICRO (1987)
Yale N. Patt, Stephen W. Melvin, Wen-mei W. Hwu, Michael Shebanow, Chein Chen
Run-time generation of HPS microinstructions from a VAX instruction stream. MICRO (1986)
Yale N. Patt, Wen-mei W. Hwu, Stephen W. Melvin, Michael Shebanow, Chein Chen, Jiajuin Wei
Experiments with HPS, a Restricted Data Flow Microarchitecture for High Performance Computers. COMPCON (1986)
Yale N. Patt, Stephen W. Melvin, Wen-mei W. Hwu, Michael Shebanow
Critical issues regarding HPS, a high performance microarchitecture. MICRO (1985)
Yale N. Patt, Wen-mei W. Hwu, Michael Shebanow
HPS, a new microarchitecture: rationale and introduction. MICRO (1985)