Tse-Yu Yeh

Publication Activity (10 Years)

Years Active: 1991-2016
Publications (10 Years): 1

Top Topics

Instruction Set

Prediction Algorithm

Top Venues

ICS 25th Anniversary

Publications

Onur Mutlu, Rich Belgard, Thomas R. Gross, Norman P. Jouppi, John L. Hennessy, Steven A. Przybylski, Chris Rowen, Yale N. Patt, Wen-mei W. Hwu, Stephen W. Melvin, Michael Shebanow, Tse-Yu Yeh, Andy Wolfe
Common Bonds: MIPS, HPS, Two-Level Branch Prediction, and Compressed Code RISC Processor. IEEE Micro 36 (4) (2016)
Tse-Yu Yeh, Deborah T. Marr, Yale N. Patt
Author retrospective for increasing the instruction fetch rate via multiple branch prediction and a branch address cache. ICS 25th Anniversary (2014)
Tse-Yu Yeh
Low-Power, High-Performance Architecture of the PWRficient Processor Family. IEEE Micro 27 (2) (2007)
Tse-Yu Yeh
Low-power, high-performance architecture of the PWRficient processor family. Hot Chips Symposium (2006)
Marius Evers, Tse-Yu Yeh
Understanding branches and designing branch predictors for high-performance microprocessors. Proc. IEEE 89 (11) (2001)
Tse-Yu Yeh, Yale N. Patt
Alternative Implementations of Two-Level Adaptive Branch Prediction. 25 Years ISCA: Retrospectives and Reprints (1998)
Tse-Yu Yeh, Yale N. Patt
Retrospective: Alternative Implementations of Two-Level Adaptive Training Branch Prediction. 25 Years ISCA: Retrospectives and Reprints (1998)
Po-Yung Chang, Eric Hao, Tse-Yu Yeh, Yale N. Patt
Branch Classification: New Mechanism for Improving Branch Predictor Performance. Int. J. Parallel Program. 24 (2) (1996)
Po-Yung Chang, Eric Hao, Tse-Yu Yeh, Yale N. Patt
Branch classification: a new mechanism for improving branch predictor performance. MICRO (1994)
Tse-Yu Yeh, Yale N. Patt
Branch history table indexing to prevent pipeline bubbles in wide-issue superscalar processors. MICRO (1993)
Tse-Yu Yeh, Yale N. Patt
A Comparison of Dynamic Branch Predictors that Use Two Levels of Branch History. ISCA (1993)
Tse-Yu Yeh, Deborah T. Marr, Yale N. Patt
Increasing the Instruction Fetch Rate via Multiple Branch Prediction and a Branch Address Cache. International Conference on Supercomputing (1993)
Tse-Yu Yeh, Yale N. Patt
A comprehensive instruction fetch mechanism for a processor supporting speculative execution. MICRO (1992)
Tse-Yu Yeh, Yale N. Patt
Alternative Implementations of Two-Level Adaptive Branch Prediction. ISCA (1992)
Tse-Yu Yeh, Yale N. Patt
Two-Level Adaptive Training Branch Prediction. MICRO (1991)
Michael Butler, Tse-Yu Yeh, Yale N. Patt, Mitch Alsup, Hunter Scales, Michael Shebanow
Single Instruction Stream Parallelism is Greater Than Two. ISCA (1991)