Low-Power, High-Performance Architecture of the PWRficient Processor Family.
Tse-Yu YehPublished in: IEEE Micro (2007)
Keyphrases
- low power
- single chip
- signal processor
- high speed
- vlsi architecture
- low power consumption
- low cost
- power consumption
- gate array
- cmos technology
- embedded dram
- computation intensive
- mixed signal
- nm technology
- high power
- real time
- cmos image sensor
- logic circuits
- vlsi circuits
- wireless transmission
- instruction set
- energy efficiency
- distributed memory
- parallel processing
- delay insensitive
- power reduction
- hardware and software
- hardware implementation
- power dissipation
- digital signal processing
- design considerations