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Common Bonds: MIPS, HPS, Two-Level Branch Prediction, and Compressed Code RISC Processor.

Onur MutluRich BelgardThomas R. GrossNorman P. JouppiJohn L. HennessySteven A. PrzybylskiChris RowenYale N. PattWen-mei W. HwuStephen W. MelvinMichael ShebanowTse-Yu YehAndy Wolfe
Published in: IEEE Micro (2016)
Keyphrases
  • instruction set
  • prediction accuracy
  • industry standard
  • application specific
  • processor core
  • prediction algorithm
  • neural network
  • data structure
  • high speed
  • parallel processing
  • low cost
  • floating point
  • error detection