Low-power, high-performance architecture of the PWRficient processor family.
Tse-Yu YehPublished in: Hot Chips Symposium (2006)
Keyphrases
- low power
- single chip
- signal processor
- high speed
- vlsi architecture
- power consumption
- low cost
- low power consumption
- gate array
- cmos technology
- mixed signal
- embedded dram
- high power
- computation intensive
- cmos image sensor
- nm technology
- wireless transmission
- real time
- parallel processing
- logic circuits
- vlsi circuits
- power reduction
- digital signal processing
- signal processing
- image sensor
- distributed memory
- instruction set
- wireless networks
- ultra low power