Marius Evers

Publication Activity (10 Years)

Years Active: 1996-2007
Publications (10 Years): 0

Publications

Jeegar Tilak Shah, Marius Evers, Jeff Trull, Alper Halbutogullari
Circuit optimization for leakage power reduction using multi-threshold voltages for high performance microprocessors. ISPD (2007)
Marius Evers, Tse-Yu Yeh
Understanding branches and designing branch predictors for high-performance microprocessors. Proc. IEEE 89 (11) (2001)
Marius Evers, Sanjay J. Patel, Robert S. Chappell, Yale N. Patt
An Analysis of Correlation and Predictability: What Makes Two-Level Branch Predictors Work. ISCA (1998)
Sanjay J. Patel, Marius Evers, Yale N. Patt
Improving Trace Cache Effectiveness with Branch Promotion and Trace Packing. ISCA (1998)
Jared Stark, Marius Evers, Yale N. Patt
Variable Length Path Branch Prediction. ASPLOS (1998)
Eric Hao, Po-Yung Chang, Marius Evers, Yale N. Patt
Increasing the Instruction Fetch Rate via Block-Structured Instruction Set Architectures. Int. J. Parallel Program. 26 (4) (1998)
Yale N. Patt, Sanjay J. Patel, Marius Evers, Daniel H. Friendly, Jared Stark
One Billion Transistors, One Uniprocessor, One Chip. Computer 30 (9) (1997)
Po-Yung Chang, Marius Evers, Yale N. Patt
Improving branch prediction accuracy by reducing pattern history table interference. Int. J. Parallel Program. 25 (5) (1997)
Po-Yung Chang, Marius Evers, Yale N. Patt
Improving branch prediction accuracy by reducing pattern history table interference. IEEE PACT (1996)
Eric Hao, Po-Yung Chang, Marius Evers, Yale N. Patt
Increasing the Instruction Fetch Rate via Block-structured Instruction Set Architectures. MICRO (1996)
Marius Evers, Po-Yung Chang, Yale N. Patt
Using Hybrid Branch Predictors to Improve Branch Prediction Accuracy in the Presence of Context Switches. ISCA (1996)