Paul Racunas

Publication Activity (10 Years)

Years Active: 1997-2022
Publications (10 Years): 7

Top Topics

Parallel Implementation

Graphics Hardware

Heterogeneous Computing

Top Venues

Publications

Michael B. Sullivan, Nirmal R. Saxena, Mike O'Connor, Donghyuk Lee, Paul Racunas, Saurabh Hukerikar, Timothy Tsai, Siva Kumar Sastry Hari, Stephen W. Keckler
Characterizing and Mitigating Soft Errors in GPU DRAM. IEEE Micro 42 (4) (2022)
Michael B. Sullivan, Nirmal R. Saxena, Mike O'Connor, Donghyuk Lee, Paul Racunas, Saurabh Hukerikar, Timothy Tsai, Siva Kumar Sastry Hari, Stephen W. Keckler
Characterizing and Mitigating Soft Errors in GPU DRAM. MICRO (2021)
Siva Kumar Sastry Hari, Paolo Rech, Timothy Tsai, Mark Stephenson, Arslan Zulfiqar, Michael B. Sullivan, Philip P. Shirvani, Paul Racunas, Joel S. Emer, Stephen W. Keckler
Estimating Silent Data Corruption Rates Using a Two-Level Model. CoRR (2020)
Richard Bramley, Yanxiang Huang, Guangshan Duan, Nirmal R. Saxena, Paul Racunas
On the Measurement of Safe Fault Failure Rates in High-Performance Compute Processors. ITC (2020)
Atieh Lotfi, Saurabh Hukerikar, Keshav Balasubramanian, Paul Racunas, Nirmal R. Saxena, Richard Bramley, Yanxiang Huang
Resiliency of automotive object detection networks on GPU architectures. ITC (2019)
Atieh Lotfi, Nirmal R. Saxena, Richard Bramley, Paul Racunas, Philip P. Shirvani
Low Overhead Tag Error Mitigation for GPU Architectures. DSN (2018)
Steven Raasch, Arijit Biswas, Jon Stephan, Paul Racunas, Joel S. Emer
A fast and accurate analytical technique to compute the AVF of sequential bits in a processor. MICRO (2015)
Arijit Biswas, Paul Racunas, Joel S. Emer, Shubhendu S. Mukherjee
Computing Accurate AVFs using ACE Analysis on Performance Models: A Rebuttal. IEEE Comput. Archit. Lett. 7 (1) (2008)
Paul Racunas, Kypros Constantinides, Srilatha Manne, Shubhendu S. Mukherjee
Perturbation-based Fault Screening. HPCA (2007)
Arijit Biswas, Paul Racunas, Razvan Cheveresan, Joel S. Emer, Shubhendu S. Mukherjee, Ram Rangan
Computing Architectural Vulnerability Factors for Address-Based Structures. ISCA (2005)
Paul Racunas, Yale N. Patt
Partitioned first-level cache design for clustered microarchitectures. ICS (2003)
Jared Stark, Paul Racunas, Yale N. Patt
Reducing the Performance Impact of Instruction Cache Misses by Writing Instructions into the Reservation Stations Out-of-Order. MICRO (1997)