Atieh Lotfi

Publication Activity (10 Years)

Years Active: 2011-2022
Publications (10 Years): 8

Top Venues

DATE

ITC

ICCD

FPGA

University of California San Diego, USA (PHD)

Education History

University of California San Diego, USA

PHD

Publications

Nirmal R. Saxena, Atieh Lotfi
Error Model (EM) - A New Way of Doing Fault Simulation. ITC (2022)
Jeng-Hau Lin, Atieh Lotfi, Vahideh Akhlaghi, Zhuowen Tu, Rajesh K. Gupta
Accelerating Local Binary Pattern Networks with Software-Programmable FPGAs. DATE (2019)
Atieh Lotfi, Saurabh Hukerikar, Keshav Balasubramanian, Paul Racunas, Nirmal R. Saxena, Richard Bramley, Yanxiang Huang
Resiliency of automotive object detection networks on GPU architectures. ITC (2019)
Atieh Lotfi, Nirmal R. Saxena, Richard Bramley, Paul Racunas, Philip P. Shirvani
Low Overhead Tag Error Mitigation for GPU Architectures. DSN (2018)
Atieh Lotfi, Rajesh K. Gupta
ReHLS: Resource-Aware Program Transformation Workflow for High-Level Synthesis. ICCD (2017)
Atieh Lotfi, Rajesh K. Gupta
RxRE: Throughput Optimization for High-Level Synthesis using Resource-Aware Regularity Extraction (Abstract Only). FPGA (2017)
Atieh Lotfi, Abbas Rahimi, Amir Yazdanbakhsh, Hadi Esmaeilzadeh, Rajesh K. Gupta
Grater: An approximation workflow for exploiting data-level parallelism in FPGA acceleration. DATE (2016)
Atieh Lotfi, Abbas Rahimi, Luca Benini, Rajesh K. Gupta
Aging-Aware Compilation for GP-GPUs. ACM Trans. Archit. Code Optim. 12 (2) (2015)
Mehdi Semsarzadeh, Atieh Lotfi, Mahmoud Reza Hashemi, Shervin Shirmohammadi
A fine-grain distortion and complexity aware parameter tuning model for the H.264/AVC encoder. Signal Process. Image Commun. 28 (5) (2013)
Atieh Lotfi, Arash Bayat, Saeed Safari
Architectural vulnerability aware checkpoint placement in a multicore processor. IOLTS (2012)
Atieh Lotfi, Parisa Kabiri, Zainalabedin Navabi
Configurable architecture for memory BIST. EWDTS (2011)

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Publication Activity (10 Years)

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Atieh Lotfi