Zainalabedin Navabi

Publication Activity (10 Years)

Years Active: 1979-2024
Publications (10 Years): 51

Top Venues

ETS

EWDTS

DTIS

DDECS

Publications

Nooshin Nosrati, Zainalabedin Navabi
Analysis and Enhancement of Resilience for LSTM Accelerators Using Residue-Based CEDs. IEEE Access 12 (2024)
Alireza Nahvy, Zainalabedin Navabi
Pico-Programmable Neurons to Reduce Computations for Deep Neural Network Accelerators. IEEE Trans. Very Large Scale Integr. Syst. 32 (7) (2024)
Zahra Hojati, Zainalabedin Navabi
A Low-Cost Combinational Approximate Multiplier. DDECS (2023)
Negin Safari, Amirmahdi Joudi, Maryam Rajabalipanah, Zahra Jahanpeima, Hasan Sadeghzadeh, Zainalabedin Navabi
HIRMA: High-Performance Implementation for RISC-V Microcontroller Applications. EWDTS (2023)
Nooshin Nosrati, Zainalabedin Navabi
A Low-cost Residue-based Scheme for Error-resiliency of RNN Accelerators. DDECS (2023)
Ebrahim Nouri, Nooshin Nosrati, Hanieh Totonchi Asl, Mozhgan Rezaie Manavand, Zainalabedin Navabi
Multi-Level Fault Injection Methodology Using UVM-SystemC. EWDTS (2023)
Katayoon Basharkhah, Raheleh Sadat Mirhashemi, Nooshin Nosrati, Mohammad-Javad Zare, Zainalabedin Navabi
Learning Electrical Behavior of Core Interconnects for System-Level Crosstalk Prediction. ETS (2023)
Nooshin Nosrati, Seyedeh Maryam Ghasemi, Mahboobe Sadeghipour Roodsari, Zainalabedin Navabi
Concurrent Error Detection for LSTM Accelerators. ETS (2022)
Mahboobe Sadeghipour Roodsari, Ebrahim Nouri, Fatemeh Sheikhshoaei, Paolo Prinetto, Zainalabedin Navabi
A Secure Canary-Based Hardware Approach Against ROP. ITASEC (2022)
Nooshin Nosrati, Maksim Jenihhin, Zainalabedin Navabi
MLC: A Machine Learning Based Checker For Soft Error Detection In Embedded Processors. IOLTS (2022)
Fatemeh Sheikh Shoaei, Alireza Nahvy, Zainalabedin Navabi
Testable Array Multipliers for a Better Utilization of C-Testability and Bijectivity. CoRR (2022)
Maryam Rajabalipanah, Mahboobe Sadeghipour Roodsari, Zahra Jahanpeima, Gianluca Roascio, Paolo Prinetto, Zainalabedin Navabi
AFTAB: A RISC-V Implementation with Configurable Gateways for Security. EWDTS (2021)
Mahsa Akhsham, Zainalabedin Navabi
Integrating an Interconnect BIST with Crosstalk Avoidance Hardware. IOLTS (2021)
Mohammad Rasoul Roshanshah, Katayoon Basharkhah, Zainalabedin Navabi
Online Testing of a Row-Stationary Convolution Accelerator. ETS (2021)
Nooshin Nosrati, Katayoon Basharkhah, Hanieh Totonchi Asl, Zahra Mahdavi, Zainalabedin Navabi
Testing a RISCV-Like Architecture With an HDL-Based Virtual Tester. DTIS (2021)
Mahboobe Sadeghipour Roodsari, Hanieh Totonchi Asl, Zainalabedin Navabi
n-DiCE-LSTM: An n-Dimensional Configurable and Efficient Architecture for LSTM Accelerator. ISVLSI (2021)
Somayeh Sadeghi Kohan, Mehdi Kamal, Zainalabedin Navabi
Self-Adjusting Monitor for Measuring Aging Rate and Advancement. IEEE Trans. Emerg. Top. Comput. 8 (3) (2020)
Mohammad Ebrahimi, Rezgar Sadeghi, Zainalabedin Navabi
LUT Input Reordering to Reduce Aging Impact on FPGA LUTs. IEEE Trans. Computers 69 (10) (2020)
Rezgar Sadeghi, Zainalabedin Navabi
Built-In Predictors for Dynamic Crosstalk Avoidance. ETS (2020)
Saba Yousefzadeh, Katayoon Basharkhah, Nooshin Nosrati, Maryam Rajabalipanah, Seyedeh Maryam Ghasemi, Zainalabedin Navabi
Reconfiguration of Embedded Accelerators by Microprogramming for Intensive Loop Computations. DDECS (2020)
Maryam Rajabalipanah, Seyedeh Maryam Ghasemi, Nooshin Nosrati, Katayoon Basharkhah, Saba Yousefzadeh, Zainalabedin Navabi
Reducing DFT hardware overhead by use of a test microprogram in a microprogrammed hardware accelerator. DFT (2020)
Mahboobe Sadeghipour Roodsari, Mohamad Ali Saber, Zainalabedin Navabi
DiBA: n-Dimensional Bitslice Architecture for LSTM Implementation. DDECS (2020)
Katayoon Basharkhah, Rezgar Sadeghi, Nooshin Nosrati, Zainalabedin Navabi
ESL, Back-annotating Crosstalk Fault Models into High-level Communication Links. VTS (2020)
Mohammad Ebrahimi, Zainalabedin Navabi
Selecting Representative Critical Paths for Sensor Placement Provides Early FPGA Aging Information. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (10) (2020)
Seyyede Maryam Ghasemy, Maryam Rajabalipanah, Saeideh Sarmadi, Zainalabedin Navabi
SCOAP-based Directed Random Test Generation for Combinational Circuits. EWDTS (2019)
Nooshin Nosrati, Katayoon Basharkhah, Rezgar Sadeghi, Zainalabedin Navabi
An ESL Environment for Modeling Electrical Interconnect Faults. ISVLSI (2019)
Rezgar Sadeghi, Nooshin Nosrati, Katayoon Basharkhah, Zainalabedin Navabi
Back-annotation of Interconnect Physical Properties for System-Level Crosstalk Modeling. ETS (2019)
Mahsa Akhsham, Atefesadat Seyedolhosseini, Zainalabedin Navabi
Test Adapted Shielding by a Multipurpose Crosstalk Avoidance Scheme. ETS (2019)
Nooshin Nosrati, Katayoon Basharkhah, Rezgar Sadeghi, Carna Zivkovic, Christoph Grimm, Zainalabedin Navabi
Making System Level Test Possible by a Mixed-mode, Multi-level, Integrated Modeling Environment. EWDTS (2019)
Saba Yousefzadeh, Katayoon Basharkhah, Nooshin Nosrati, Rezgar Sadeghi, Jaan Raik, Maksim Jenihhin, Zainalabedin Navabi
An Accelerator-based Architecture Utilizing an Efficient Memory Link for Modern Computational Requirements. EWDTS (2019)
Samira Ahmadi Farsani, Katayoon Basharkhah, Amin Mohaghegh, Zainalabedin Navabi
From Abstract Modeling of ADAS Applications to an Accelerator-based Hardware Realization. EWDTS (2019)
Reza Sharafinejad, Bijan Alizadeh, Zainalabedin Navabi
Automatic Correction of Dynamic Power Management Architecture in Modern Processors. IEEE Trans. Very Large Scale Integr. Syst. 26 (2) (2018)
Ramin Rezaeizadeh Rookerd, Somayeh Sadeghi Kohan, Zainalabedin Navabi
Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture. ACM Great Lakes Symposium on VLSI (2018)
Fatemeh Refan, Bijan Alizadeh, Zainalabedin Navabi
Scalable Symbolic Simulation-Based Automatic Correction of Modern Processors. IEEE Trans. Very Large Scale Integr. Syst. 26 (10) (2018)
Somayeh Sadeghi Kohan, Arash Vafaei, Zainalabedin Navabi
Near-Optimal Node Selection Procedure for Aging Monitor Placement. IOLTS (2018)
Fatemeh Refan, Bijan Alizadeh, Zainalabedin Navabi
Bridging Presilicon and Postsilicon Debugging by Instruction-Based Trace Signal Selection in Modern Processors. IEEE Trans. Very Large Scale Integr. Syst. 25 (7) (2017)
Elaheh Sadredini, Mohammad Hashem Haghbayan, Mahmood Fathy, Zainalabedin Navabi
Test Generation and Scheduling for a Hybrid BIST Considering Test Time and Power Constraint. CoRR (2017)
Zana Ghaderi, Mohammad Ebrahimi, Zainalabedin Navabi, Eli Bozorgzadeh, Nader Bagherzadeh
SENSIBle: A Highly Scalable SENsor DeSIgn for Path-Based Age Monitoring in FPGAs. IEEE Trans. Computers 66 (5) (2017)
Elaheh Sadredini, Mohammadreza Najafi, Mahmood Fathy, Zainalabedin Navabi
BILBO-friendly Hybrid BIST Architecture with Asymmetric Polynomial Reseeding. CoRR (2017)
Shaghayegh Vahdat, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram, Zainalabedin Navabi
TruncApp: A truncation-based approximate divider for energy efficient DSP applications. DATE (2017)
Farzaneh Zokaee, Hossein Sabaghian Bidgoli, Vahid Janfaza, Payman Behnam, Zainalabedin Navabi
A novel SAT-based ATPG approach for transition delay faults. HLDVT (2017)
Hossein Sabaghian Bidgoli, Payman Behnam, Bijan Alizadeh, Zainalabedin Navabi
Reducing Search Space for Fault Diagnosis: A Probability-Based Scoring Approach. ISVLSI (2017)
Rasool Sharifi, Zainalabedin Navabi
Online Profiling for cluster-specific variable rate refreshing in high-density DRAM systems. ETS (2017)
Elaheh Sadredini, Reza Rahimi, Paniz Foroutan, Mahmood Fathy, Zainalabedin Navabi
An Improved Scheme for Pre-computed Patterns in Core-based SoC Architecture. CoRR (2017)
Seyedeh Hanieh Hashemi, Reza Namazian, Zainalabedin Navabi
Optimistic clock adjustment for preventing Better-than-worst-case violations. VLSI-SoC (2016)
Morteza Soltani, Mohammad Ebrahimi, Zainalabedin Navabi
Prolonging Lifetime of Non-volatile Last Level Caches with Cluster Mapping. ACM Great Lakes Symposium on VLSI (2016)
Arezoo Kamran, Zainalabedin Navabi
Self-Healing Many-Core Architecture: Analysis and Evaluation. VLSI Design 2016 (2016)
Hamed Najafi Haghi, Mikhail M. Chupilko, Alexander S. Kamkin, Zainalabedin Navabi
ESL design with RTL-verified predesigned abstract communication channels. EWDTS (2016)
Maksim Jenihhin, Alexander Kamkin, Zainalabedin Navabi, Somayeh Sadeghi Kohan
Universal mitigation of NBTI-induced aging by design randomization. EWDTS (2016)
Elaheh Sadredini, Reza Rahimi, Paniz Foroutan, Mahmood Fathy, Zainalabedin Navabi
An improved scheme for pre-computed patterns in core-based SoC architecture. EWDTS (2016)
Arezoo Kamran, Zainalabedin Navabi
Stochastic testing of processing cores in a many-core architecture. Integr. 55 (2016)
Zainalabedin Navabi
HDLs evolve as they affect design methodology for a higher abstraction and a better integration. DTIS (2015)
Samaneh Ghandali, Bijan Alizadeh, Masahiro Fujita, Zainalabedin Navabi
Automatic High-Level Data-Flow Synthesis and Optimization of Polynomial Datapaths Using Functional Decomposition. IEEE Trans. Computers 64 (6) (2015)
Hasan Sohofi, Zainalabedin Navabi
System-level assertions: approach for electronic system-level verification. IET Comput. Digit. Tech. 9 (3) (2015)
Fatemeh Refan, Bijan Alizadeh, Zainalabedin Navabi
Signature oriented model pruning to facilitate multi-threaded processors debugging. VTS (2015)
Samaneh Ghandali, Bijan Alizadeh, Zainalabedin Navabi
Low power scheduling in high-level synthesis using dual-Vth library. ISQED (2015)
Amirreza Nekooei, Zainalabedin Navabi
Multi-valued logic test access mechanism for test time and power reduction. DTIS (2015)
Mehran Goli, Amin Ghasemazar, Zainalabedin Navabi
Application-specific power-aware mapping for reconfigurable NoC architectures. DTIS (2015)
Somayeh Sadeghi Kohan, Arezoo Kamran, Farnaz Forooghifar, Zainalabedin Navabi
Aging in digital circuits and age monitoring: Object-oriented modeling and evaluation. DTIS (2015)
Elmira Karimi, Mohammad Hashem Haghbayan, Amir-Mohammad Rahmani, Mahmoud Tabandeh, Pasi Liljeberg, Zainalabedin Navabi
Accelerated On-chip Communication Test Methodology Using a Novel High-Level Fault Model. MCSoC (2015)
Mohammad Hashem Haghbayan, Amir-Mohammad Rahmani, Mohammad Fattah, Pasi Liljeberg, Juha Plosila, Zainalabedin Navabi, Hannu Tenhunen
Power-aware online testing of manycore systems in the dark silicon era. DATE (2015)
Mohammad Ansari, Hassan Afzali-Kusha, Behzad Ebrahimi, Zainalabedin Navabi, Ali Afzali-Kusha, Massoud Pedram
A near-threshold 7T SRAM cell with high write and read margins and low write time for sub-20 nm FinFET technologies. Integr. 50 (2015)
Shahrzad Keshavarz, Amirreza Nekooei, Zainalabedin Navabi
Preemptive multi-bit IJTAG testing with reconfigurable infrastructure. DFT (2014)
Parastoo Kamranfar, Ali Shahabi, Ghazaleh Vazhbakht, Zainalabedin Navabi
Configurable Systolic Matrix Multiplication. VLSI Design (2014)
Samaneh Ghandali, Bijan Alizadeh, Masahiro Fujita, Zainalabedin Navabi
RTL datapath optimization using system-level transformations. ISQED (2014)
Hasan Sohofi, Zainalabedin Navabi
Assertion-based verification for system-level designs. ISQED (2014)
Arezoo Kamran, Zainalabedin Navabi
Homogeneous many-core processor system test distribution and execution mechanism. ETS (2014)
Payman Behnam, Bijan Alizadeh, Zainalabedin Navabi
Automatic correction of certain design errors using mutation technique. ETS (2014)
Somayeh Sadeghi Kohan, Payman Behnam, Bijan Alizadeh, Masahiro Fujita, Zainalabedin Navabi
Improving polynomial datapath debugging with HEDs. ETS (2014)
Marzieh Mohammadi, Somayeh Sadeghi Kohan, Nasser Masoumi, Zainalabedin Navabi
An off-line MDSI interconnect BIST incorporated in BS 1149.1. ETS (2014)
Paniz Foroutan, Mehdi Kamal, Zainalabedin Navabi
A heuristic path selection method for small delay defects test. DFT (2014)
Najmeh Farajipour Ghohroud, Zainalabedin Navabi
Back-annotation of gate-level power properties into system level descriptions. NEWCAS (2014)
Farimah Farahmandi, Bijan Alizadeh, Zainalabedin Navabi
Effective Combination of Algebraic Techniques and Decision Diagrams to Formally Verify Large Arithmetic Circuits. ISVLSI (2014)
Payman Behnam, Hossein Sabaghian Bidgoli, Bijan Alizadeh, Kamyar Mohajerani, Zainalabedin Navabi
A probabilistic approach for counterexample generation to aid design debugging. EWDTS (2013)
Arezoo Kamran, Vahid Janfaza, Zainalabedin Navabi
Extracting complete set of equations to analyze VHDL-AMS descriptions. EWDTS (2013)
Mohammad Mirzaei, Mahmoud Tabandeh, Bijan Alizadeh, Zainalabedin Navabi
A New Approach for Automatic Test Pattern Generation in Register Transfer Level Circuits. IEEE Des. Test 30 (4) (2013)
Arezoo Kamran, Zainalabedin Navabi
Online periodic test mechanism for homogeneous many-core processors. VLSI-SoC (2013)
Somayeh Sadeghi Kohan, Shahrzad Keshavarz, Farzaneh Zokaee, Farimah Farahmandi, Zainalabedin Navabi
A new structure for interconnect offline testing. EWDTS (2013)
M. H. Haghbayan, Saeed Safari, Zainalabedin Navabi
Power constraint testing for multi-clock domain SoCs using concurrent hybrid BIST. DDECS (2012)
Mohammadreza Najafi, Saeed Safari, Zainalabedin Navabi
Soft Error Analysis on Communication Channels in On-Chip Communication Networks. DSD (2012)
Samaneh Ghandali, Bijan Alizadeh, Zainalabedin Navabi, Masahiro Fujita
and algebraic techniques. MEMOCODE (2012)
Somayeh Sadeghi Kohan, Majid Namaki-Shoushtari, Fatemeh Javaheri, Zainalabedin Navabi
BS 1149.1 extensions for an online interconnect fault detection and recovery. ITC (2012)
Reza Nakhjavani, Ali Shahabi, Saeed Safari, Zainalabedin Navabi
A novel graceful degradable routing algorithm for 3D on-chip networks. INA-OCMC@HiPEAC (2012)
Parisa Kabiri, Zainalabedin Navabi
Effective RT-level software-based self-testing of embedded processor cores. DDECS (2012)
Hossein Sabaghian Bidgoli, Majid Namaki-Shoushtari, Zainalabedin Navabi
A Probabilistic and Constraint Based Approach for Low Power Test Generation. Asian Test Symposium (2012)
Atieh Lotfi, Parisa Kabiri, Zainalabedin Navabi
Configurable architecture for memory BIST. EWDTS (2011)
Nastaran Nemati, Zainalabedin Navabi
Adaptation of Standard RT Level BIST Architectures for System Level Communication Testing. Asian Test Symposium (2011)
Behnam Khodabandeloo, Seyyed Alireza Hoseini, Sajjad Taheri, Mohammad Hashem Haghbayan, Mahmood Reza Babaei, Zainalabedin Navabi
Online Test Macro Scheduling and Assignment in MPSoC Design. Asian Test Symposium (2011)
Fatemeh Javaheri, Majid Namaki-Shoushtari, Parastoo Kamranfar, Zainalabedin Navabi
Mapping Transaction Level Faults to Stuck-At Faults in Communication Hardware. Asian Test Symposium (2011)
M. H. Haghbayan, Sara Karamati, Fatemeh Javaheri, Zainalabedin Navabi
Test Pattern Selection and Compaction for Sequential Circuits in an HDL Environment. Asian Test Symposium (2010)
Niki Shakeri, Nastaran Nemati, Majid Nili Ahmadabadi, Zainalabedin Navabi
Near optimal machine learning based random test generation. EWDTS (2010)
Pejman Lotfi-Kamran, Amir-Mohammad Rahmani, Masoud Daneshtalab, Ali Afzali-Kusha, Zainalabedin Navabi
EDXY - A low cost congestion-aware routing algorithm for network-on-chips. J. Syst. Archit. 56 (7) (2010)
Ali Shahabi, S. Behdad Hosseini, Hasan Sohofi, Zainalabedin Navabi
A partitioning approach to improve reconfigurable neuron-inspired online BIST. IOLTS (2010)
Amirali Ghofrani, Fatemeh Javaheri, Saeed Safari, Zainalabedin Navabi
Automatic selection of efficient observability points in combinational gate level circuits using particle swarm optimization. SoC (2010)
Arezoo Kamran, Mohammad Saeed Jahangiry, Zainalabedin Navabi
Merit based directed random test generation (MDRTG) scheme for combinational circuits. EWDTS (2010)
Amirali Ghofrani, Fatemeh Javaheri, Zainalabedin Navabi
Assertion based verification in TLM. EWDTS (2010)
Nastaran Nemati, Majid Namaki-Shoushtari, Zainalabedin Navabi
A mixed HDL/PLI test package. EWDTS (2010)
M. H. Haghbayan, Zainalabedin Navabi
Architecture design and technical methodology for bus testing. EWDTS (2010)
Arezoo Kamran, Nastaran Nemati, Somayeh Sadeghi Kohan, Zainalabedin Navabi
Virtual tester development using HDL/PLI. EWDTS (2010)
Mohammad Reza Jamali, Masood Deh-Yadegari, Arash Arami, Caro Lucas, Zainalabedin Navabi
Real-time embedded emotional controller. Neural Comput. Appl. 19 (1) (2010)

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Publication Activity (10 Years)

Top Topics

Top Venues

Zainalabedin Navabi