Bijan Alizadeh

Publication Activity (10 Years)

Years Active: 2003-2024
Publications (10 Years): 52

Top Topics

Formal Verification

Digital Circuits

Functional Decomposition

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

IEEE Trans. Very Large Scale Integr. Syst.

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Mohammad Moradi Shahmiri, Bijan Alizadeh
Concealing Exposed Circuit Features Through a MaxSAT-Based Logic Locking Method. IEEE Trans. Circuits Syst. II Express Briefs 71 (4) (2024)
Ali Falahati, Mahdieh Shamirzaee, Bijan Alizadeh
An FPGA-Based Hardware Architecture for P + M Class PMU Using Accuracy-Aware O-Spline Filter Selection and Modulation Detection. IEEE Trans. Instrum. Meas. 73 (2024)
Hamed Hossein-Talaee, Ali Jahanian, Bijan Alizadeh
Systematic Trojan Detection in Crypto-Systems Using the Model Checker. J. Circuits Syst. Comput. 33 (3) (2024)
Bijan Alizadeh, Masoud Shiroei
Automatic correction of RTL designs using a lightweight partial high level synthesis. Integr. 91 (2023)
Abolfazl Sajadi, Ahmad Shabani, Bijan Alizadeh
DC-PUF: Machine learning-resistant PUF-based authentication protocol using dependency chain for resource-constraint IoT devices. J. Netw. Comput. Appl. 217 (2023)
Amir Ashtari, Ahmad Shabani, Bijan Alizadeh
A comparative study of machine learning classifiers for secure RF-PUF-based authentication in internet of things. Microprocess. Microsystems 93 (2022)
Amir Ashtari, Ahmad Shabani, Bijan Alizadeh
Mutual Lightweight PUF-Based Authentication Scheme Using Random Key Management Mechanism for Resource-Constrained IoT Devices. ISC Int. J. Inf. Secur. 14 (3) (2022)
Fatemeh Khormizi, Ahmad Shabani, Bijan Alizadeh
Hardware Patching Methodology for Neutralizing Timing Hardware Trojans Using Vulnerability Analysis and Time Borrowing Scheme. IEEE Trans. Circuits Syst. II Express Briefs 69 (6) (2022)
Negar Aghapour Sabbagh, Bijan Alizadeh
Arithmetic Circuit Correction by Adding Optimized Correctors Based on Groebner Basis Computation. ETS (2021)
Mohammad Sabri, Ahmad Shabani, Bijan Alizadeh
SAT-Based Integrated Hardware Trojan Detection and Localization Approach Through Path-Delay Analysis. IEEE Trans. Circuits Syst. II Express Briefs 68 (8) (2021)
Mohammad Hashemi, Bijan Alizadeh
FPGA-based Implementation of a New Data Frame Correction System for Merging Units. CoRR (2021)
Ahmad Shabani, Bijan Alizadeh
Enhancing Hardware Trojan Detection Sensitivity Using Partition-Based Shuffling Scheme. IEEE Trans. Circuits Syst. II Express Briefs 68 (1) (2021)
Siamack BeigMohammadi, Bijan Alizadeh
Combinational Hybrid Signal Selection With Updated Reachability Lists for Post-Silicon Debug. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (1) (2020)
Bijan Alizadeh, Yasaman Abadi
Incremental SAT-Based Correction of Gate Level Circuits by Reusing Partially Corrected Circuits. IEEE Trans. Circuits Syst. (12) (2020)
Ahmad Shabani, Bijan Alizadeh
PODEM: A low-cost property-based design modification for detecting Hardware Trojans in resource-constraint IoT devices. J. Netw. Comput. Appl. 167 (2020)
Ali Azarmi Gilan, Mohammad Emad, Bijan Alizadeh
FPGA-Based Implementation of a Real-Time Object Recognition System Using Convolutional Neural Network. IEEE Trans. Circuits Syst. II Express Briefs (4) (2020)
Ahmad Shabani, Bijan Alizadeh
PMTP: A MAX-SAT-Based Approach to Detect Hardware Trojan Using Propagation of Maximum Transition Probability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (1) (2020)
Amir Ashtari, Ahmad Shabani, Bijan Alizadeh
A New RF-PUF Based Authentication of Internet of Things Using Random Forest Classification. ISCISC (2019)
Bijan Alizadeh, Seyyed Reza Sharafinejad
Incremental SAT-Based Accurate Auto-Correction of Sequential Circuits Through Automatic Test Pattern Generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38 (2) (2019)
Mehrnaz Ahmadi, Sahand Salamat, Bijan Alizadeh
A Dynamic Timing Error Avoidance Technique Using Prediction Logic in High-Performance Designs. IEEE Trans. Very Large Scale Integr. Syst. 27 (3) (2019)
Mojtaba Abbasnezhad, Bijan Alizadeh
FPGA-Based Implementation of an Artificial Neural Network for Measurement Acceleration in BOTDA Sensors. IEEE Trans. Instrum. Meas. 68 (11) (2019)
Masoud Shiroei, Bijan Alizadeh, Masahiro Fujita
Data-path aware high-level ECO synthesis. Integr. 65 (2019)
Bijan Alizadeh, Mehdi Shakeri
QBF-Based Post-Silicon Debug of Speed-Paths Under Timing Variations. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2018)
Reza Sharafinejad, Bijan Alizadeh, Zainalabedin Navabi
Automatic Correction of Dynamic Power Management Architecture in Modern Processors. IEEE Trans. Very Large Scale Integr. Syst. 26 (2) (2018)
Fatemeh Refan, Bijan Alizadeh, Zainalabedin Navabi
Scalable Symbolic Simulation-Based Automatic Correction of Modern Processors. IEEE Trans. Very Large Scale Integr. Syst. 26 (10) (2018)
Sahand Salamat, Mohammad Reza Azarbad, Bijan Alizadeh
High-Level Synthesis of Non-Rectangular Multi-Dimensional Nested Loops Using Reshaping and Vectorization. ICRC (2018)
Fatemeh Refan, Bijan Alizadeh, Zainalabedin Navabi
Bridging Presilicon and Postsilicon Debugging by Instruction-Based Trace Signal Selection in Modern Processors. IEEE Trans. Very Large Scale Integr. Syst. 25 (7) (2017)
Mahdieh Grailoo, Bijan Alizadeh, Behjat Forouzandeh
Improved Range Analysis in Fixed-Point Polynomial Data-Path. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36 (11) (2017)
Shayan Moini, Bijan Alizadeh, Mohammad Emad, Reza Ebrahimpour
A Resource-Limited Hardware Accelerator for Convolutional Neural Networks in Embedded Vision Applications. IEEE Trans. Circuits Syst. II Express Briefs (10) (2017)
Alireza Mahzoon, Bijan Alizadeh
OptiFEX: A Framework for Exploring Area-Efficient Floating Point Expressions on FPGAs With Optimized Exponent/Mantissa Widths. IEEE Trans. Very Large Scale Integr. Syst. 25 (1) (2017)
Mehrnaz Ahmadi, Bijan Alizadeh, Behjat Forouzandeh
A Hybrid Time Borrowing Technique to Improve the Performance of Digital Circuits in the Presence of Variations. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2017)
Sahand Salamat, Mehrnaz Ahmadi, Bijan Alizadeh, Masahiro Fujita
Systematic approximate logic optimization using don't care conditions. ISQED (2017)
Hossein Sabaghian Bidgoli, Payman Behnam, Bijan Alizadeh, Zainalabedin Navabi
Reducing Search Space for Fault Diagnosis: A Probability-Based Scoring Approach. ISVLSI (2017)
Alireza Mahzoon, Bijan Alizadeh
Systematic Design Space Exploration of Floating-Point Expressions on FPGA. IEEE Trans. Circuits Syst. II Express Briefs (3) (2017)
Mohammad Reza Azarbad, Bijan Alizadeh
Scalable SMT-Based Equivalence Checking of Nested Loop Pipelining in Behavioral Synthesis. ACM Trans. Design Autom. Electr. Syst. 22 (2) (2017)
Payman Behnam, Bijan Alizadeh, Sajjad Taheri
Automated Formal Equivalence Verification of Pipelined Nested Loops in Datapath Designs. CoRR (2017)
Mahdieh Grailoo, Bijan Alizadeh, Behjat Forouzandeh
UAFEA: Unified Analytical Framework for IA/AA-Based Error Analysis of Fixed-Point Polynomial Specifications. IEEE Trans. Circuits Syst. II Express Briefs (10) (2016)
Hossein Mehri, Bijan Alizadeh
Genetic-Algorithm-Based FPGA Architectural Exploration Using Analytical Models. ACM Trans. Design Autom. Electr. Syst. 22 (1) (2016)
Siamack BeigMohammadi, Bijan Alizadeh
Combinational trace signal selection with improved state restoration for post-silicon debug. DATE (2016)
Payman Behnam, Bijan Alizadeh, Sajjad Taheri, Masahiro Fujita
Formally analyzing fault tolerance in datapath designs using equivalence checking. ASP-DAC (2016)
Mohammad Hashem Haghbayan, Bijan Alizadeh
A dynamic specification to automatically debug and correct various divider circuits. Integr. 53 (2016)
Samaneh Ghandali, Bijan Alizadeh, Masahiro Fujita, Zainalabedin Navabi
Automatic High-Level Data-Flow Synthesis and Optimization of Polynomial Datapaths Using Functional Decomposition. IEEE Trans. Computers 64 (6) (2015)
Alireza Mahzoon, Bijan Alizadeh
Multi-objective Optimization of Floating Point Arithmetic Expressions Using Iterative Factorization. ISVLSI (2015)
Fatemeh Refan, Bijan Alizadeh, Zainalabedin Navabi
Signature oriented model pruning to facilitate multi-threaded processors debugging. VTS (2015)
Samaneh Ghandali, Bijan Alizadeh, Zainalabedin Navabi
Low power scheduling in high-level synthesis using dual-Vth library. ISQED (2015)
Payman Behnam, Bijan Alizadeh
In-Circuit Mutation-Based Automatic Correction of Certain Design Errors Using SAT Mechanisms. ATS (2015)
Reza Sharafinejad, Bijan Alizadeh, Masahiro Fujita
UPF-based formal verification of low power techniques in modern processors. VTS (2015)
Mehrzad Nejat, Bijan Alizadeh, Ali Afzali-Kusha
Dynamic Flip-Flop Conversion: A Time-Borrowing Method for Performance Improvement of Low-Power Digital Circuits Prone to Variations. IEEE Trans. Very Large Scale Integr. Syst. 23 (11) (2015)
Farimah Farahmandi, Bijan Alizadeh
Groebner basis based formal verification of large arithmetic circuits using Gaussian elimination and cone-based polynomial extraction. Microprocess. Microsystems 39 (2) (2015)
Mehrnaz Ahmadi, Bijan Alizadeh, Behjat Forouzandeh
A Timing Error Mitigation Technique for High Performance Designs. ISVLSI (2015)
Hossein Mehri, Bijan Alizadeh
Analytical performance model for FPGA-based reconfigurable computing. Microprocess. Microsystems 39 (8) (2015)
Bijan Alizadeh, Payman Behnam, Somayeh Sadeghi Kohan
A Scalable Formal Debugging Approach with Auto-Correction Capability Based on Static Slicing and Dynamic Ranking for RTL Datapath Designs. IEEE Trans. Computers 64 (6) (2015)
Samaneh Ghandali, Bijan Alizadeh, Masahiro Fujita, Zainalabedin Navabi
RTL datapath optimization using system-level transformations. ISQED (2014)
Mohammad Hashem Haghbayan, Bijan Alizadeh, Amir-Mohammad Rahmani, Pasi Liljeberg, Hannu Tenhunen
Automated formal approach for debugging dividers using dynamic specification. DFT (2014)
Ehsan Qasemi, Amir Samadi, Mohammad H. Shadmehr, Bardia Azizian, Sajjad Mozaffari, Amir Shirian, Bijan Alizadeh
Highly scalable, shared-memory, Monte-Carlo tree search based Blokus Duo Solver on FPGA. FPT (2014)
M. H. Haghbayan, Bijan Alizadeh, Payman Behnam, Saeed Safari
Formal Verification and Debugging of Array Dividers with Auto-correction Mechanism. VLSI Design (2014)
Vahid Janfaza, Payman Behnam, Bahjat Forouzandeh, Bijan Alizadeh
A Low-Power Enhanced Bitmask-Dictionary Scheme for Test Data Compression. ISVLSI (2014)
Payman Behnam, Bijan Alizadeh, Zainalabedin Navabi
Automatic correction of certain design errors using mutation technique. ETS (2014)
Somayeh Sadeghi Kohan, Payman Behnam, Bijan Alizadeh, Masahiro Fujita, Zainalabedin Navabi
Improving polynomial datapath debugging with HEDs. ETS (2014)
Mehrzad Nejat, Bijan Alizadeh, Ali Afzali-Kusha
Dynamic Flip-Flop conversion to tolerate process variation in low power circuits. DATE (2014)
Farimah Farahmandi, Bijan Alizadeh, Zainalabedin Navabi
Effective Combination of Algebraic Techniques and Decision Diagrams to Formally Verify Large Arithmetic Circuits. ISVLSI (2014)
Payman Behnam, Hossein Sabaghian Bidgoli, Bijan Alizadeh, Kamyar Mohajerani, Zainalabedin Navabi
A probabilistic approach for counterexample generation to aid design debugging. EWDTS (2013)
Mohammad Mirzaei, Mahmoud Tabandeh, Bijan Alizadeh, Zainalabedin Navabi
A New Approach for Automatic Test Pattern Generation in Register Transfer Level Circuits. IEEE Des. Test 30 (4) (2013)
Bijan Alizadeh, Payman Behnam
Formal equivalence verification and debugging techniques with auto-correction mechanism for RTL designs. Microprocess. Microsystems 37 (8-D) (2013)
Bijan Alizadeh
A formal approach to debug polynomial datapath designs. ASP-DAC (2012)
Bijan Alizadeh, Masahiro Fujita
A functional test generation technique for RTL datapaths. HLDVT (2012)
Samaneh Ghandali, Bijan Alizadeh, Zainalabedin Navabi, Masahiro Fujita
and algebraic techniques. MEMOCODE (2012)
Bijan Alizadeh
Formal Verification and Debugging of Precise Interrupts on High Performance Microprocessors. ACM Trans. Design Autom. Electr. Syst. 17 (4) (2012)
Bijan Alizadeh, Masahiro Fujita
Early case splitting and false path detection to improve high level ATPG techniques. ISCAS (2011)
Bijan Alizadeh, Masahiro Fujita
Debugging and optimizing high performance superscalar out-of-order processors using formal verification techniques. ISQED (2011)
Bijan Alizadeh, Masahiro Fujita
Modular equivalence verification of polynomial datapaths with multiple word-length operands. HLDVT (2011)
Finn Haedicke, Bijan Alizadeh, Görschwin Fey, Masahiro Fujita, Rolf Drechsler
Polynomial datapath optimization using constraint solving and formal modelling. ICCAD (2010)
Bijan Alizadeh, Mohammad Mirzaei, Masahiro Fujita
Coverage Driven High-Level Test Generation Using a Polynomial Model of Sequential Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (5) (2010)
Amir Masoud Gharehbaghi, Bijan Alizadeh, Masahiro Fujita
Aggressive overclocking support using a novel timing error recovery technique on FPGAs (abstract only). FPGA (2010)
Bijan Alizadeh, Masahiro Fujita
Guided gate-level ATPG for sequential circuits using a high-level test generation approach. ASP-DAC (2010)
Bijan Alizadeh, Masahiro Fujita
Modular Datapath Optimization and Verification Based on Modular-HED. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (9) (2010)
Bijan Alizadeh, Masahiro Fujita
A debugging method for repairing post-silicon bugs of high performance processors in the fields. FPT (2010)
Bijan Alizadeh, Amir Masoud Gharehbaghi, Masahiro Fujita
Pipelined Microprocessors Optimization and Debugging. ARC (2010)
Omid Sarbishei, Mahmoud Tabandeh, Bijan Alizadeh, Masahiro Fujita
A Formal Approach for Debugging Arithmetic Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28 (5) (2009)
Bijan Alizadeh, Masahiro Fujita
Modular arithmetic decision procedure with auto-correction mechanism. HLDVT (2009)
Omid Sarbishei, Bijan Alizadeh, Masahiro Fujita
Polynomial datapath optimization using partitioning and compensation heuristics. DAC (2009)
Bijan Alizadeh, Masahiro Fujita
Improved heuristics for finite word-length polynomial datapath optimization. ICCAD (2009)
Bijan Alizadeh, Masahiro Fujita
A Unified Framework for Equivalence Verification of Datapath Oriented Applications. IEICE Trans. Inf. Syst. (5) (2009)
Omid Sarbishei, Mahmoud Tabandeh, Bijan Alizadeh, Masahiro Fujita
High-level optimization of integer multipliers over a finite bit-width with verification capabilities. MEMOCODE (2009)
Bijan Alizadeh, Masahiro Fujita
Sequential Equivalence Checking Using a Hybrid Boolean-Word Level Decision Diagram. CSICC (2008)
Omid Sarbishei, Bijan Alizadeh, Masahiro Fujita
Arithmetic Circuits Verification without Looking for Internal Equivalences. MEMOCODE (2008)
Bijan Alizadeh, Masahiro Fujita
A novel formal approach to generate high-level test vectors without ILP and SAT solvers. HLDVT (2007)
Bijan Alizadeh, Masahiro Fujita
Automatic Merge-Point Detection for Sequential Equivalence Checking of System-Level and RTL Descriptions. ATVA (2007)
Bijan Alizadeh
Word level functional coverage computation. ASP-DAC (2006)
Arash Hooshmand, Saeed Shamshiri, Mohammad Alisafaee, Bijan Alizadeh, Pejman Lotfi-Kamran, Mostafa Naderi, Zainalabedin Navabi
Binary Taylor diagrams: an efficient implementation of Taylor expansion diagrams. ISCAS (1) (2005)
Bijan Alizadeh, Zainalabedin Navabi
Property Checking based on Hierarchical Integer Equations. ACSD (2004)
Bijan Alizadeh, Zainalabedin Navabi
Using Integer Equations to Check PSL Properties in RT Level Design. IWSOC (2004)
Bijan Alizadeh, Mohammad Reza Kakoee
Using Integer Equations for High Level Formal Verification Property Checking. ISQED (2003)