Incremental SAT-Based Correction of Gate Level Circuits by Reusing Partially Corrected Circuits.

Bijan Alizadeh Yasaman Abadi

Published in: IEEE Trans. Circuits Syst. (2020)

Keyphrases

cmos technology
analog circuits
delay insensitive
high speed
analog vlsi
logic synthesis
low power
knowledge base
low cost
higher level
circuit design
asynchronous circuits