An FPGA-Based Hardware Architecture for P + M Class PMU Using Accuracy-Aware O-Spline Filter Selection and Modulation Detection.
Ali FalahatiMahdieh ShamirzaeeBijan AlizadehPublished in: IEEE Trans. Instrum. Meas. (2024)
Keyphrases
- hardware architecture
- hardware implementation
- detection accuracy
- detection rate
- hardware architectures
- field programmable gate array
- detection algorithm
- false positives
- processing elements
- computer vision
- least squares
- object detection
- neural network
- signal detection
- associative memory
- efficient implementation
- b spline
- low cost
- real time
- nonlinear filters
- artificial intelligence
- matched filter
- data processing