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Formal Verification and Debugging of Array Dividers with Auto-correction Mechanism.
M. H. Haghbayan
Bijan Alizadeh
Payman Behnam
Saeed Safari
Published in:
VLSI Design (2014)
Keyphrases
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formal verification
program slicing
model checking
symbolic model checking
model checker
bounded model checking
automated verification
temporal logic
functional verification
orders of magnitude