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M. H. Haghbayan
Publication Activity (10 Years)
Years Active: 2010-2014
Publications (10 Years): 0
Top Topics
Formal Verification
Test Set
Constraint Solving
Concurrent Programs
Top Venues
EWDTS
DDECS
VLSI Design
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Publications
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M. H. Haghbayan
,
Bijan Alizadeh
,
Payman Behnam
,
Saeed Safari
Formal Verification and Debugging of Array Dividers with Auto-correction Mechanism.
VLSI Design
(2014)
Vahid Janfaza
,
Paniz Foroutan
,
Bahjat Forouzandeh
,
M. H. Haghbayan
A mathematical model for estimating acceptable ratio of test patterns.
EWDTS
(2014)
Elmira Karimi
,
Mahmoud Tabandeh
,
M. H. Haghbayan
Test data compression strategy while using hybrid-BIST methodology.
EWDTS
(2013)
M. H. Haghbayan
,
Saeed Safari
,
Zainalabedin Navabi
Power constraint testing for multi-clock domain SoCs using concurrent hybrid BIST.
DDECS
(2012)
M. H. Haghbayan
,
Sara Karamati
,
Fatemeh Javaheri
,
Zainalabedin Navabi
Test Pattern Selection and Compaction for Sequential Circuits in an HDL Environment.
Asian Test Symposium
(2010)
M. H. Haghbayan
,
Zainalabedin Navabi
Architecture design and technical methodology for bus testing.
EWDTS
(2010)