Amir Masoud Gharehbaghi

Publication Activity (10 Years)

Years Active: 2007-2020
Publications (10 Years): 25

Top Topics

Generation Method

Formal Verification

Eliminating Redundant

Reconfigurable Architecture

Top Venues

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.

Publications

Masahiro Fujita, Yusuke Kimura, Xingming Le, Yukio Miyasaka, Amir Masoud Gharehbaghi
Synthesis and Optimization of Multiple Portions of Circuits for ECO based on Set-Covering and QBF Formulations. DATE (2020)
Peikun Wang, Amir Masoud Gharehbaghi, Masahiro Fujita
A Logic Optimization Method by Eliminating Redundant Multiple Faults from Higher to Lower Cardinality. IPSJ Trans. Syst. LSI Des. Methodol. 13 (2020)
Peikun Wang, Amir Masoud Gharehbaghi, Masahiro Fujita
An Automatic Test Pattern Generation Method for Multiple Stuck-At Faults by Incrementally Extending the Test Patterns. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (10) (2020)
Akihiro Goda, Yukio Miyasaka, Amir Masoud Gharehbaghi, Masahiro Fujita
Synthesis and Generalization of Parallel Algorithms Considering Communication Constraints. ISQED (2020)
Peikun Wang, Amir Masoud Gharehbaghi, Masahiro Fujita
An Incremental Automatic Test Pattern Generation Method for Multiple Stuck-at Faults. VTS (2019)
Peikun Wang, Amir Masoud Gharehbaghi, Masahiro Fujita
Automatic Test Pattern Generation for Double Stuck-at Faults Based on Test Patterns of Single Faults. ISQED (2019)
Heming Sun, Zhengxue Cheng, Amir Masoud Gharehbaghi, Shinji Kimura, Masahiro Fujita
Approximate DCT Design for Video Encoding Based on Novel Truncation Scheme. IEEE Trans. Circuits Syst. I Regul. Pap. (4) (2019)
Yusuke Kimura, Amir Masoud Gharehbaghi, Masahiro Fujita
Signal Selection Methods for Debugging Gate-Level Sequential Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2019)
Qinhao Wang, Amir Masoud Gharehbaghi, Takeshi Matsumoto, Masahiro Fujita
High-Level Engineering Change Through Programmable Datapath and SMT Solvers. ISCAS (2019)
Tomohiro Maruoka, Yukio Miyasaka, Akihiro Goda, Amir Masoud Gharehbaghi, Masahiro Fujita
Live Demonstration: Automatic Synthesis of Algorithms on Multi Chip/FPGA with Communication Constraints. ISCAS (2019)
Yusuke Kimura, Amir Masoud Gharehbaghi, Masahiro Fujita
Signal Selection Methods for Efficient Multi-Target Correction. ISCAS (2019)
Qi Lu, Amir Masoud Gharehbaghi, Masahiro Fujita
Approximate Arithmetic Circuit Design Using a Fast and Scalable Method. VLSI-SoC (2019)
Yusuke Kimura, Amir Masoud Gharehbaghi, Masahiro Fujita
C Description Reconstruction Method from a Revised Netlist for ECO Support. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2018)
Peikun Wang, Conrad J. Moore, Amir Masoud Gharehbaghi, Masahiro Fujita
An ATPG Method for Double Stuck-At Faults by Analyzing Propagation Paths of Single Faults. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2018)
Amir Masoud Gharehbaghi, Tomohiro Maruoka, Masahiro Fujita
A New Reconfigurable Architecture with Applications to IoT and Mobile Computing. IFIPIoT@WCC (2018)
Heming Sun, Zhengxue Cheng, Amir Masoud Gharehbaghi, Shinji Kimura, Masahiro Fujita
A low-cost approximate 32-point transform architecture. ISCAS (2017)
Conrad J. Moore, Peikun Wang, Amir Masoud Gharehbaghi, Masahiro Fujita
Test pattern generation for multiple stuck-at faults not covered by test patterns for single faults. ISCAS (2017)
Amir Masoud Gharehbaghi, Masahiro Fujita
A new approach for selecting inputs of logic functions during debug. ISQED (2017)
Amir Masoud Gharehbaghi, Masahiro Fujita
A new approach for diagnosing bridging faults in logic designs. ISCAS (2017)
Amir Masoud Gharehbaghi, Masahiro Fujita
A new approach for constructing logic functions after ECO. VLSI-SoC (2017)
Kentaro Iwata, Amir Masoud Gharehbaghi, Mehdi Baradaran Tahoori, Masahiro Fujita
Post Silicon Debugging of Electrical Bugs Using Trace Buffers. ATS (2017)
Amir Masoud Gharehbaghi, Masahiro Fujita
Fast and Efficient Signature-Based Sub-Circuit Matching. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2016)
Amir Masoud Gharehbaghi, Masahiro Fujita
A New Approach for Debugging Logic Circuits without Explicitly Debugging Their Functionality. ATS (2016)
Amir Masoud Gharehbaghi, Masahiro Fujita
Efficient signature-based sub-circuit matching. VLSI-SoC (2015)
Shridhar Choudhary, Amir Masoud Gharehbaghi, Takeshi Matsumoto, Masahiro Fujita
Trace signal selection methods for post silicon debugging. VLSI-SoC (2015)
Amir Masoud Gharehbaghi, Masahiro Fujita
Automatic Rectification of Processor Design Bugs Using a Scalable and General Correction Model. IEICE Trans. Inf. Syst. (4) (2014)
Amir Masoud Gharehbaghi, Masahiro Fujita
Specification and formal verification of power gating in processors. ISQED (2014)
Satoshi Jo, Amir Masoud Gharehbaghi, Takeshi Matsumoto, Masahiro Fujita
Rectification of advanced microprocessors without changing routing on FPGAs (abstract only). FPGA (2013)
Satoshi Jo, Amir Masoud Gharehbaghi, Takeshi Matsumoto, Masahiro Fujita
Debugging processors with advanced features by reprogramming LUTs on FPGA. FPT (2013)
Amir Masoud Gharehbaghi, Masahiro Fujita
Error Model Free Automatic Design Error Correction of Complex Processors Using Formal Methods. Asian Test Symposium (2012)
Amir Masoud Gharehbaghi, Masahiro Fujita
Transaction-based post-silicon debug of many-core System-on-Chips. ISQED (2012)
Amir Masoud Gharehbaghi, Masahiro Fujita
Automatic rectification of design errors in complex processors with programmable hardware. FPT (2012)
Amir Masoud Gharehbaghi, Masahiro Fujita
Transaction Ordering in Network-on-Chips for Post-Silicon Validation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2012)
Amir Masoud Gharehbaghi, Masahiro Fujita
Global transaction ordering in Network-on-Chips for post-silicon validation. ISQED (2011)
Amir Masoud Gharehbaghi, Masahiro Fujita
Formal verification guided automatic design error diagnosis and correction of complex processors. HLDVT (2011)
Amir Masoud Gharehbaghi, Bijan Alizadeh, Masahiro Fujita
Aggressive overclocking support using a novel timing error recovery technique on FPGAs (abstract only). FPGA (2010)
Bijan Alizadeh, Amir Masoud Gharehbaghi, Masahiro Fujita
Pipelined Microprocessors Optimization and Debugging. ARC (2010)
Masahiro Fujita, Yoshihisa Kojima, Amir Masoud Gharehbaghi
Debugging from high level down to gate level. DAC (2009)
Amir Masoud Gharehbaghi, Masahiro Fujita
Transaction-based debugging of system-on-chips with patterns. ICCD (2009)
Hassan Hatefi-Ardakani, Amir Masoud Gharehbaghi, Shaahin Hessabi
Timing verification of distributed network systems at higher levels of abstraction. HLDVT (2008)
Hassan Hatefi-Ardakani, Amir Masoud Gharehbaghi, Shaahin Hessabi
System-Level Assertion-Based Performance Verification for Embedded Systems. CSICC (2008)
Amir Masoud Gharehbaghi, Benyamin Hamdin Yaran, Shaahin Hessabi, Maziar Goudarzi
An assertion-based verification methodology for system-level design. Comput. Electr. Eng. 33 (4) (2007)